Retargeting IP -> Effective designs eye next generation
Effective designs eye next generation
By Aparna Dey, Director of IP Reuse Products, and Services, Cadence Design Systems Inc., San Jose, Calif., EE Times
March 26, 2001 (3:12 p.m. EST)
The advent of nanometer process technologies has enabled the system-on-chip (SoC) generation, and each advance in process technology offers an opportunity to increase the level of integration. While that capability creates new opportunities, rising gate counts and shrinking device dimensions add to the complexity and magnitude of the design problem. The most direct way to meet this challenge is to reuse intellectual-property (IP) blocks from existing designs and third-party vendors.
The IP blocks must be designed with reuse in mind, however. Adherence to company standards and industry standards such as the Virtual Socket Interface (VSI) increases confidence that IP blocks from internal and third-party sources will function correctly when connected. Design of IP for reuse can increase design effort by as much as three times, so designers must choose their battles wisely.
IP can be packaged for reuse at many stages in the desi gn cycle, such as the behavioral, register-transfer level (RTL) or GDSII levels. Soft IP-an archived, synthesizable HDL description-may be targeted to any process, but its use entails more verification time and more time spent on back-end placement and routing of blocks. Soft IP is relatively flexible, since it is easier to modify RTL code than to change a placed and routed layout. The trade-off with soft IP is that it allows process and design flexibility but has only moderate time-to-market benefits.
Reusing hard IP
Hard IP is archived after completion of functional verification and place and route. Since verification typically accounts for about 70 percent of design time, reuse of hard IP offers corresponding time savings.
But hard IP is tied to a specific process technology, so it allows for very little alteration. That means that the benefits of hard IP diminish when a design is migrated to a new process. Furthermore, hard IP reuse entails an area overhead, since block-based design is typically less areaefficient than flat design, and it is difficult to shrink routed blocks with existing technology.
Hard IP can come from within a company or from external vendors. Memory blocks, for example, are typically implemented as hard IP. Many vendors of off-chip DRAM components now also provide embedded DRAM as hard IP targeted to specific processes.
Parametric IP offers a compromise between the flexibility of soft IP and the time savings of hard IP. A parametric block is a composite of hard and soft sub-blocks. The soft section has the flexibility to allow modification to suit a new design, and the already verified hard section saves design time.
Most IP reuse today is at the RTL level, although designers are moving increasingly toward hard IP reuse. Industry analysts predict a dramatic increase in embedded software reuse, which dictates a fi xed platform and, therefore, hard IP reuse between revisions of a product. Most of the functionality of these products is implemented in software, so the platform-based designs feature a high percentage of reusable IP. A move from one revision of a design to another involves changing the software that runs on the hardware platform and typically implements a new feature or fixes a bug from a previous revision.
The introduction of a product often coincides with a move to a new process technology. In addition to adding features to products, migration to a new process technology affords the opportunity to optimize performance, power consumption and area usage. But migration also requires regression from the use of hard IP to soft IP. In moving to a completely new process technology, perhaps only 30 percent of the design (the memory blocks, for example) is implemented as hard IP. Soft IP is hardened over the life of a product, so the hard IP content of a design may rise to 85 percent at the end of the product's life cycle, before the design is again migrated to a new process. Designers must be able to archive reusable blocks as hard or soft IP and must have a way to select hard or soft IP for reuse based on the product's position in its life cycle.
When a product is migrated to a new process technology, designers must fall back to using soft IP for their proprietary blocks and go through the place and route and timing verification processes for the new technology. However, third-party IP may be available that is already optimized for the new process technology. Use of third-party IP cores reduces time-to-market when a product is migrated to a new process because designers need not go through verification and back-end design for these blocks. It is therefore advantageous if designers have a way to select among IP blocks from internal and external sources.
Uniform standards help
For effective reuse, IP blocks must be designed up front with reuse in mind. Good design p ractices reduce the overhead inherent in designing reusable IP. These practices can combine external standards, such as those from VSI, with a company's internal guidelines.
Implementing uniform design standards across an entire organization ensures that any design team can reuse IP. Designers, when presented with a selection of potentially thousands of IP blocks, must be able to make their selection with confidence that blocks have been designed and archived according to these standards.
Companies manage hundreds or thousands of IP blocks, including multiple derivatives. An efficient Web-based IP management system provides a safe means to archive and access this data. It offers a uniform view of IP blocks, regardless of whether they are internally authored or drawn from external vendors. IP management is a time-to-market tool, as it gives the means to reuse-rather than rebuild-major system blocks. It also provides a better way of integrating IP from diverse sources. It offers a way to build company standards into the archiva. A Web-based IP management system provides a simple way to implement and maintain these standards. It also ensures that everyone follows the same guidelines and that IP is properly registered in the system.
Archived blocks may be as complex as a DSP or microcontroller core, or as simple as a block extracted from a hierarchical design. An archival system requires a host of supporting information, with as many as 40 associated files for each IP block. This includes test data and documentation, and design data at numerous levels, such as software blocks and embedded operating systems. An easily accessible IP management system provides an intuitive means to control and maintain this huge library of data. Moreover, building version control and bug tracking into the system ensures that designers have access to the correct versions of blocks.
Use of a Web-based IP management system also breaks down potential barriers b etween design teams, allowing designers to share data freely and to confidently use IP, knowing it conforms to company guidelines.
A flexible search engine allows designers to locate IP by customizable attributes, key words and categories. Once a designer has located the correct block, the system downloads the block and its associated files to a local directory for inspection and use by the designer.
IP management systems may also track the use of archived blocks, such as which IP blocks are used in a particular product and, conversely, in which products a particular IP block is used. This gives an extra incentive to package blocks as reusable IP, since the authors of IP blocks can easily determine the extent of a block's reuse within an organization. Effective Web-based IP management also includes security features that protect archived IP by restricting access to particular system features or groups of IP. Blocks tagged with information about the author of the IP make it easy to deter mine a block's owner, while encrypting IP prevents unauthorized use.
IP reuse is a survival decision. The increased level of integration allowed by successive generations of process geometries means that today's chip will be tomorrow's IP block. Designers must be able to make informed decisions regarding the choice of IP blocks for reuse, and a Web-based IP management system facilitates those decisions.