FPGAs advance, but verification challenges increase
Update: GateRocket Inc. has ceased operations (August 2011)
Dave Orecchio, GateRocket
10/18/2010 5:04 AM EDT
If there is one overriding success story in the semiconductor industry at the present time, it’s the exploding use of programmable logic devices (PLDs) in general, and field-programmable gate arrays (FPGAs) in particular.
The current state-of-the-art FPGA devices at the 45/40 nm technology node boast hundreds of thousands of look-up-tables (LUTs), thousands of DSP cores, multi-mega-bits of memory, and thousands of general-purpose input/output (GPIO) pins coupled with a humongous serial I/O bandwidth. These devices are now making their presence felt in a vast range of applications across multiple market segments, including aerospace and defense; automotive, broadcast, and consumer; high-performance computing (HPC); industrial, scientific, and medical; and wired and wireless communications.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Dynamic Memory Allocation and Fragmentation in C and C++
- PCIe error logging and handling on a typical SoC
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)