One of the primary advantages of using programmable-logic devices (PLDs) is that they provide a hardware platform on which it is possible to do software development, modeling, system-level simulation, intellectual property (IP) and co-verification very early in the design process. A new category of products is emerging that combines the flexibility and time-to-market advantages of programmable logic with predesigned standard processor cores, memory and peripherals in the design of complex systems-on-chip (SoC) that were not possible in the past. These devices require a new class of design-entry and simulation tools as well as high-speed, cycle-accurate behavioral models of the various IP blocks.
The gradual increase in size, speed and complexity of PLDs wasn't enough to enable system-on-a-programmable chip (SoPC) design for the masses. Something else was required: accessible, easy-to-use embedded processor cores and other IP, in the form of either hard macros or soft cores, to offer flexibility and time-to-market advantages not possible with an application-specific integrated circuits (ASICs). These predesigned cores, which can be easily instantiated and simulated within an SoPC design, speed the overall design process by eliminating the need for lengthy internal development or securing of third-party IP licenses.
Whether a processor is a soft, synthesizable core that can be implemented in a PLD or a hard macro that is already laid out, the eventual performance, size and power specifications of the final design, and each implementation approach, will have its own design flow requirements. When doing processor-based design, one of the basic requirements is having access to a cycle-accurate instruction set simulator (ISS). An ISS is commonly available for standard embedded processor cores, such as those offered by MIPS Technologies and ARM Ltd. Examples include execution-driven simulators that execute instructions and model their perform ance in a particular application; or event-based simulators that can provide performance statistics and profiling, as well as trace files that contain cycle-by-cycle information about the instructions. The ISS may not be fast enough for certain applications and oftentimes, actual processors in hardware evaluation boards are used for debug (using their debug ports).
To resolve system-level problems, it is important to have accurate and complete models of how a processor core interacts with memory, other devices and I/O units. When designing with a hard-macro processor, a bus functional model of the processor is often required. Such a model describes the particular system bus operations, timing and interface to the other blocks within an SoC design. When designing with a soft processor core, it's also necessary to have the appropriate behavioral models to verify that the processor subsystem's timing specifications are being met in the actual physical PLD implementation. Access to high-level support of VHDL or Verilog simulation of the register-transfer-level code of the entire PLD-based SoC design is required. In addition, support for behavioral simulation and VHDL and Verilog testbenches is necessary.
For system software development, it is important that an embedded processor-based solution be fully supported by a standard software tools design suite consisting of a compiler, debugger, assembler, linker, loader and any necessary support libraries and utilities. Industry-standard architectures, such as MIPS and ARM, offer a wide selection of both real-time operating system (RTOS) support, as well as software tool chain support for system software development.Tasks in parallel
It is clear that SoPC design requires a design methodology that ties together the ability to do system software development in parallel with the traditional PLD synthesis, simulation and place-and-route requirements, along with being able to model and debug embedded processors and other IP blocks.
Many semiconductor companies now provide a complete software solution for implementing both soft-core and hard-processor macro-based SoPC designs easily. For example, Altera offers a 32-bit soft-core RISC embedded processor called NIOS, capable of up to 50-Mips performance and optimized for implementation in its PLD product lines. Excalibur MIPS- and ARM-based hard-core products integrate peripherals, such as timers, UARTs, interrupt controllers and external memory interfaces, along with trace capability, and on-chip single-port and dual-port SRAM in a embedded processor "stripe" that is adjacent to an Apex 20-K PLD structure of various size options.
In an example of an Excalibur hard-core implementation that uses the ARM922T processor core, the basic embedded processor stripe is implemented along with varying amounts of on-chip single- and dual-port SRAM and corresponding sizes of PLD structures, giving designers several options from which to choose. Altera provides a cycle-accurate model of th e embedded processor stripe that can be used for simulation.
The company provides internally developed soft cores in its Megacore function portfolio as well as optimized cores developed by third-party partners through the Altera Megafunctions Partners Program (AMPP). Megafunctions include cores for DSP, networking communications, PCI controllers and peripherals, and includes dense drive support. Both Excalibur MIPS and ARM-based products use the industry-standard Advanced Microcontroller Bus Architecture (Amba) high-performance bus (AHB) to interface with Altera Megacores or AMPP partner IP cores.
The SoPC Builder is a graphical user interface (GUI)-based tool that is used to facilitate system design. Most systems consist of various IP modules that are interconnected via buses.
With the SoPC Builder, designers can choose the modules required and use the MegaWizard GUI interface to select different parameters for each module as well as the different clock domains. The SoPC Builder then generates the synthesizable code for each module, generates the buses, configures the processor and also provides a simulation model.
Third-party synthesis tools are used to generate a gate-level netlist. Altera's Quartus software takes the resulting gate-level netlist and does the actual place and route and design implementation within the PLD structure. The SoPC Builder can also be used to generate C-code header files and peripheral drivers that can be used in a standard, embedded software-development suite.
Both the Excalibur ARM and MIPS-based products support a logic analyzer megafunction called Signal-Tap that is provided with the Quartus software. SignalTap is a parameterized embedded logic analyzer that provides access to signals within the PLD structure through the IEEE Std. 1149.1 Joint Test Action Group (JTAG) circuitry. It captures signals from the internal nodes while the device is running and can use the PLD embedded system block RAM to store acquisition data. A designer can an alyze internal logic at speed without bringing internal signals to the I/O pins.
The Excalibur MIPS-based product supports an enhanced JTAG port that can be hooked up to third-party vendor solutions to allow for software debug, the setting of breakpoints and single stepping through code. ARM source-level debuggers for debugging applications written in C++, C or assembly language in a Windows-based or Unix environment support the Excalibur ARM-based products. Embedded ICE logic that provides standard run control debug features is available as well.
The embedded ICE unit is controlled using a JTAG port. This logic can be programmed to generate breakpoints, stopping the processor and causing it to enter a debug state. There, memory and register contents can be examined or modified, images can be loaded and code can be stepped through. The ARM core also supports an embedded trace macrocell, which monitors the ARM system buses and passes compressed information through a trace port to a trace port analyzer, an external device that stores information from the trace port. The debug tools retrieve the data from the analyzer and reconstruct a history of the processor's activity. The trace display includes symbol information and links to the source code being debugged. The embedded trace macrocell is also controlled via a JTAG port.
SoPC solutions will revolutionize the way designers do microprocessor-based designs, by enabling cost-effective access to state-of-the-art technology, design flexibility and higher system-level performance than what was possible in the past. System designers will no longer have to secure their own processor and/or other IP cores and licenses, incur high nonrecurring engineering charges and wafer mask costs, or suffer through lengthy development cycle times of doing a cell-based ASIC design. Having the flexibility to make changes during development or production is extremely compelling from a time-to-market perspective, especially in applications where industry standards and/or algorithms are in a state of flux (e.g., third-generation wireless basestations).
What is essential to the emergence and adoption of these new SoPC solutions is providing a complete set of integrated hardware and software that enables system-software development, IP block integration, design entry, modeling, simulation, debug capability and synthesis in a cohesive and easy-to-use design environment.