Tools For Reprogrammability -> Reuse forces embedded programming
Reuse forces embedded programming
Reuse forces embedded programming
By Joe Mastroianni, Vice President, Product Development, Adaptive Silicon Inc., Santa Clara, Calif, EE Times
November 20, 2000 (11:31 a.m. EST)
IC fabrication capabilities are enabling complex system-chip development, thereby potentially lowering die and system costs while increasing system performance. At the same time, mounting system complexity is raising the level of project risk, driving up both verification cycle requirements and costs. The emerging trend toward multimillion gate, system-chip development brings the industry to the conclusion that discrete reprogrammable logic should be the next target for system-chip integration.
Implementing high-risk design blocks in embedded programmable logic will reduce project schedules. Embedded programmable logic will also enable field upgrades of complex algorithms or of blocks implementing protocols for evolving standards.
As process geometries continue to shrink and engineering, mask and prototype silicon costs rise, embedded reprogrammable logic will make it possible to build multiple product versions from a single die, le veraging those costs over multiple products. Like many simple ideas, though, implementation brings a Gordian knot of issues that thus far has repelled most adventurers.
Integration of reprogrammable logic calls for a novel application of tools and systems, as well as changing some of the core "culture" and practices of engineering teams. The perceived high expense of discovering solutions to these problems has stifled well-known attempts to bring embedded reprogrammable technology to market. Discrete component vendors are stymied by unfamiliar issues such as how to close chip-level timing, how to adapt commercial synthesis tools to coexist in both a system-on-chip (SoC) design flow and a reprogramming flow, and how to adapt to ASIC and application-specific standard product (ASSP) physical design environments. As with most quantum jumps in technology, this development presents challenges that engineering teams can readily overcome by making the necessary cultural shifts as well as putting ne w technology to use. The solutions, though not immediately obvious, are well within the reach of most SoC and ASIC design teams.
Oddly enough, the biggest obstacle to finding these solutions is usually identifying the problems themselves. Design teams that are characteristically "siloed" into targeted technology areas trade perspective for productivity. Industry trends, stereotypically grouped under "Moore's Law," tear down classical design-team divisions of labor, which means responsibilities must be repartitioned. We saw such an effect with the so-called deep-submicron discontinuity in the mid-1990s. The task of handling technical issues driven by deep-submicron wiring parasitics paled in comparison to the psychological repartitioning of work that was necessary to realize designs. Today, hardly a designer remembers the times when wiring delays were presumed negligible and crossta lk analyses were a black art.
But similar psychological barriers will have to be transcended in order to embed reprogrammable logic into ASIC and off-the-shelf ASSP designs. This time, we will bridge the disciplines of silicon design and system-level reprogrammability. The key here, as it was in the deep-submicron "crisis" of the '90s, is to bring together engineers with the appropriate backgrounds to solve the problem in a unified design environment. It's important that the silicon team and the system design team learn what questions they need to ask-and they can do this only by interacting with each other.
To start, project management must abandon its outdated pattern of hiring and assemble a team of professionals with suitable backgrounds in systems, circuits and silicon design. Once this is done, the group will undoubtedly spend its first meeting debating the only initial common ground all parties share: the impossibility of attaining chip-level timing closure with reprogrammabl e logic. ASIC and ASSP engineers who have only recently adopted true hierarchical methods will need to deal with a volume of additional circuitry and attendant issues sure to dwarf those they face with DRAM, sense amps and decode logic. Embedded programmable logic is not only a greater portion of silicon's circuitry-it also has to be factored into calculations at levels of abstraction in ASIC and ASSP design that are both unusual and discouraged.
Here arises the first emotional design crisis: Chip-design houses have burned-in design flows they are loathe to change for fear of breaking the holiest of engineering holies"-that which is not broken."
To date, no ASIC/ASSP vendor has come out of that initial timing debate with a solution in hand. Declaring the problem too expensive to solve, they've successfully adopted the marketing position that embedded reprogrammability is unfeasible and, consequently, unnecessary.
But this stance ignores the obvious success of an entire multi billion-dollar electronics industry and its use of discrete reprogrammable components. Silicon design teams have proven in many instances that design problems are no less solvable at the silicon level than at the board level. The only impediment is the reluctance to enter the inner sanctum and make the changes that are clearly tied to business survival.
Chip-level timing can now be achieved with reprogrammable logic on ASICs. Some modification to the design process is necessary, but these are unrelated to specific EDA tools or models. Instead, it is a matter of the specific use models and treatment of that design data. The only acceptable process is one that systematically integrates the programmable logic into the full chip design and test methodologies.
Presuming our hypothetical design team survives its first crisis in confidence and creates a plan to close timing, its next hurdle will be to ensure compatibility with existing EDA tools for block-level floor planning and P&R. Here, the team will grapple with some fundamental make-or-break issues.
Reprogrammable logic is characterized by its routing intensity: the more general purpose an array, the richer the required routing. Ignoring high-resistance local paths, ASIC processes today support only four or five layers of interconnect, a fact that hamstrings many classical FPGA-style designs. If a standard ASIC/ASSP manufacturing process cannot be accommodated, the team is pretty much at the "game over" stage.
In addition, ASIC P&R tools produce much more satisfactory results if channels can be provided to allow for routing over the block. The unpredictability of automatic over-the-cell routing simply needs to be taken into account in the reprogrammable logic design.
While the timing and physical-design subteams debate the merits of having volunteered, or having been volunteered for this work, the system-level team is overcoming language barriers with the silicon-implementation team. It is clear to the engineers with a background in silicon implementation that this technology is useful and that, while new and initially challenging, embedding programmable logic adds a level of flexibility most existing system-chip applications require. But it is clearly evident to the systems people that while shoehorning a reprogrammable block onto a chip may work in some applications, up-front partitioning at the register-transfer level (RTL) provides maximum benefit. The systems people will add design-margin parameters to the silicon implementers' vocabulary and will figure it into block capacity calculations. Testing woes
The team member charged with test strategy will regale the group with stories of how difficult it is to test reprogrammable circuitry and will either demand an inquiry into the feasibility of testing parts with reprogrammable logic, or will wash his hands of the project and demand that his parameters be met, without offering a solution. He will remind the team members that traditional methods won' t work and that the reprogrammable block should be tested independently from the rest of the chip-possibly through a built-in self-test technique.
Sooner or later, the marketing team will realize the product they are offering is not simply another block in the IP portfolio of in-house design engineers. Reprogrammability can be extended to the end user, an enabling capability that could drive changes in the overall business landscape. Both the marketing and technology teams realize they're now dealing with two EDA flows and, unlike traditional component providers, they need to master both of them.
The design team has been grappling with the well-understood chip-design flow and how to adapt it to this new capability. However, an EDA flow may also be provided post-silicon that allows the end user of the ASIC/ASSP (or the system into which the ASIC/ASSP is designed) to implement a circuit at an abstract level and reprogram the chip in the field. This reprogramming flow must behave in a predictabl e way consistent with the flow used to implement the ASIC/ASSP itself.
As with any new technology, the role of embedded reprogrammable logic will evolve as the implementation team learns to adapt itself to the technical and business implications this flexibility provides.
The numerous attempts at embedding reprogrammable logic onto single-chip designs, though undocumented publicly, has long been a part of silicon engineering lore. Until recently, it had been regarded as one of those things that "just won't work." That's changing, though, because the need for such a design exists, as does the ability to meet that need.
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