Can tools keep up with programmable silicon?

Can tools keep up with programmable silicon?
By Michael Santarini, EE Times
October 27, 2000 (2:01 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001027S0018

SAN MATEO, Calif. — As silicon architects crank out bigger and faster programmable devices, EDA vendors and the PLD companies' own tool divisions are scrambling to put the tools and methodologies in place that will let designers program the new parts quickly.

FGPA design starts have shot past gate arrays and ASICs in recent years on the strength of the FPGA's vaunted time-to-market advantages. But with the latest FPGAs reaching multimillion-gate counts, and with clock rates becoming a primary concern, the devices' tool flows are looking more like high-end, HDL-based ASIC or system-on-chip flows. That has implications for the FPGA's time-to-market edge.

"Even though [PLD vendors] lie by a factor of 4 to 6 about the amount of gates they really have, they've still got a whole lot of gates," said Gary Smith, Dataquest's chief EDA analyst. "In the old days, FPGAs were small enough that you could sit down, program the device and plug it into the system to see that it worked, rather than doing simulation. Now you can't do that; you have to simulate FPGAs."

FPGA tool vendors also set a precedent in the early days that's come back to haunt them, Smith said. "FPGA guys offer tools for free or damn close to free, plus they don't put much money into tool development — [instead] they buy companies," he said. "Users don't want to pay for FPGA tools, and the effective word on the Street is that there isn't any money in third-party programmable tools."

Smith said PLD vendors have "prevented the market for third-party tools from taking off" at a time when users need high-end tools the most.

Not surprisingly, executives from Xilinx Inc., Altera Corp. and the EDA companies that support them don't share Smith's views. They assert that the PLD tool flow will maintain its time-to-market advantage, even as silicon innovations push well into the millions of gates and hundreds of MHz. But most sources concede that the tool chain in most cases will r equire HDL-centric ASIC and system-on-chip (SoC) skill sets and methodologies if designs are to be completed on time.

Meanwhile, the world of PLD design is poised to open to software engineers. Xilinx next month will announce the commercial debut of its Java synthesis technology, gained via its acquisition of the LavaLogic business unit of TSI TelSys Corp.

"The FPGA market is really remarkable," said Anne Sanquini, senior vice president and general manager of Mentor Graphics Corp.'s HDL Design Division. "It wasn't too long ago that the programmable area was thought of as glue logic: You laid out your boards, did your ASICs and added your big ASSP chips, then whatever else you had left you did it on one or more FPGAs for time-to-market-vs.-cost reasons.

"This isn't your grandmother's FPGA. Time-to-market is now, more than ever, king. And with the new, monster FPGA chips, plus the ability to get decent frequency out of them, the design choice is quite different."

Ron Hawkins, chief operating officer at imaging and video capture systems company Visicom, heads a group using high-gate-count FPGAs for SoC design. Hawkins is a vocal proponent of the HDL flow and the use of large FPGAs for production.

"We've designed a real-time imaging card used in commercial machine vision [for] semiconductor wafer inspection, electronics manufacturing and medical imaging, and scientific imaging," Hawkins said. "We use Xilinx FPGAs to implement reconfigurable application-specific processors for these applications."

HDL-only policy

Hawkins two years ago implemented an "HDL-only" policy for his group and put a design-for-reuse strategy in place. "We are designing a memory interface unit for a new imaging card and are trying to completely parameterize this thing so that it is going to be reusable in other applications," he said. "It takes a bit more time, but the benefits down the road are going to be huge."

Hawkins said that the company counts on silicon processes to expand Xilinx device gate counts and that it expects to take a design from one device generation, transfer it to a next-generation FPGA and use the leftover space for new functionality.

Most sources agreed that HDLs have replaced the "schematic-sauruses" — those who hand-tweaked gates and flip-flops to get the maximum performance out of FPGAs. Philip Freidin, a longtime schematic-saurus, said that he has begun to incorporate HDLs into his methodologies.

"It isn't because I wanted to do it; it is because customers demand it," said Freidin, who specializes in high-performance FPGA design at Fliptronics (Sunnyvale, Calif.). "The issue simply comes down to design time."

Even high-performance FPGAs have large portions of synthesized blocks, Freidin said. "I still do a lot of schematic-based floor planning for high-performance areas," he said.

"High-end programmable devices are taking off," said Brian Lewis, director and principal semiconductor analyst at r esearch firm Dataquest. "PLD gate counts have reached the meat of the ASIC market; the clock rates have also increased. But vendors still have to work on driving the cost down."

Lewis cited preliminary results of an unpublished Dataquest survey of 500 system designers showing that the use of high-gate-count FPGAs is indeed on the rise. In 1999, 22 percent of respondents had reached a maximum gate count of 200,000 gates; this year, the number maxing out at 200k-gate designs is expected to be 33 percent. And the percentage of users designing FPGAs greater than 200,000 gates is expected to move from last year's 10 percent to 21 percent for 2000.

Dave Greenfield, director of development-tool marketing at Altera, acknowledged that customers' tool demands are rising in tandem with gate counts. "Users are saying, 'You need to fit your tools into our methodology, or we are not going to use you.' It is very different from just a few years ago, when a PAL user moving up the ladder loved the fact that we offere d an integrated MAX+Plus tool that had absolutely everything in one integrated environment.

"In some respects, having this great integrated package is no longer relevant for a lot of our customers," Greenfield said. "What is important is integration with third-party tools, getting performance quickly and getting a product out quickly."

Users said that while the FPGA design flow looks ever more like the ASIC flow, FPGAs will always have one advantage.

"FPGAs are far more forgiving," said John Cooley, an independent third-party ASIC and FPGA designer. "ASIC mask costs are in the hundreds of thousands to millions of dollars. Every ASIC designer I know gets on his knees and prays the moment the ASIC leaves his hands, because he knows if there is a problem it's gonna cost a whole lot of money to fix it. If you mess up on an FPGA, it isn't as big a deal; you fix it and try it again."

But expect even "fixing it and trying it again" to get more time-consuming in the near future, especially as Xilinx 's Virtex II and Altera's Apex lines, leveraging shrinking silicon processes, reach into the tens of millions of gates. PLD vendors are thus acting now to bring advanced forms of verification into their tool flows.

Greenfield said some Altera customers are using behavioral simulation and testbench capabilities from Mentor's Modelsim simulator in their flows.

Meanwhile, Xilinx, which also offers simulation, is looking at formal verification for its future tool offerings, having recently purchased French formal verification company Veriphia, which provides an equivalence checker called Tornado.

"We are examining the possibilities of this technology in our future flows," said Richard Sevcik, senior vice president of software at Xilinx (San Jose, Calif.).

Others said they think it will be a while before tools as advanced as equivalence checkers make it into FPGA suites.

"Our customers are starting to ask about more exotic verification techniques, like formal verification, but it's not mainstr eam," said Altera's Greenfield. "Formal verification certainly offers benefits in the ASIC approach, but it is not entirely clear how it can be leveraged effectively in the PLD space."

Mike Dini, owner of 12-engineer design house The Dini Group, doesn't see a need for formal verification in FPGA design. "The worst that could happen if I [program] a chip is that it won't work," said Dini. "That is not fatal, as it would be with an ASIC. If you do an ASIC, do whatever's necessary to get it right on the first try. Half-assed isn't an acceptable philosophy for an ASIC."

But Dini, who designs with both Xilinx's and Altera's biggest parts, does use FPGA simulation more often today than in previous years. "When you are designing a Virtex 2000e, there are 38,000 flip-flops in that thing. The cowboy style of design, where you blow it and see what it does — you can still do that, to a certain extent, but not too much."

"I used to argue that if you were doing an FPGA and you got it right the first time you weren't working fast enough, because there is no down side to getting an FPGA wrong other than losing a few days," he said. "I used to argue that you simulate until it gets really hard to simulate, and then blow the thing and see if it works. These days, I'm not sure that is the case."

Both Sevcik and Greenfield said that with device performance a primary concern, customers are also using static timing analysis tools in high-end FPGA design.