Silicon as task configurations
Silicon as task configurations
Silicon as task configurations
By Anthony Cataldo, EE Times
April 26, 2002 (11:50 a.m. EST)
In the late 1990s, a number of chip companies started to seriously consider the idea of embedding bits of programmable logic into an otherwise-hardwired piece of silicon-a job somewhat akin to taking out an insurance policy: For enduring a hit on die area, power and speed, the ASIC could remain malleable even after it came out of the fab. An unexpected change in a communications standard, for example, could be solved by programming the loose logic elements in the system or in the field.
Others saw the technique as a way to create one-size-fits-all platform chips. A laser printer manufacturer, for instance, could use dense and fast ASIC gates for heavy lifting, such as image compression, and then tailor the rest of the device to fit different models and features by reprogramming the FPGA portion.
However, so far, embedded FPGAs have proved a major disappointment to those who bet on the technology. The biggest culprits: difficulties reconciling hardware and software differences between ASICs and FPGAs, plus a risk-averse customer base. As a result, some of the early backers say they have put their efforts on hold, and others have come up with more modest ways to achieve some of the same goals.
In retrospect, the technology carried warning signs from the start. Even as the idea first began to gain traction, field-programmable gate array vendors remained uncertain whether such devices would undermine their own standard-parts businesses, and few could come to grips with the technical challenges of marrying disparate architectures and design flows.
That opened the way for a crop of startups keen to make good on the promise. Adaptive Silicon, an outgrowth of National Semiconductor Corp., developed an embedded FPGA based on arithmetic logic units. And variations on this configurable-logic core theme have been propose d by startups
eASIC, Leopard Logic and Systolix.
Indeed, the concept was so compelling that some well-established companies began to place bets on it, too. ASIC powerhouse LSI Logic Corp. made an investment in Adaptive Silicon and last year announced its Liquid Logic program, incorporating Adaptive's technology in LSI's cell-based ASIC methodology. Actel Corp. also got into the act last year, when it announced Varicore, a family of SRAM-based FPGA cores that could be licensed and manufactured at leading foundries. Leading FPGA vendor Xilinx Inc. hinted that it was considering licensing its FPGA technology for similar purposes.
LSI Logic worked with Ericsson on a prototype part that used the FPGA portion as a slave to a DSP, but the device never was produced in volume. This disappointment was one of the reasons LSI Logic stopped promoting its Liquid Logic program, introduced for its 0.18-micron ASIC process. "It's going to be more of a suck from customers than a push from us," said Ro nnie Vasishta, vice president of technical marketing for LSI Logic.
Actel, for its part, also acknowledged that customers have shown little interest in its Varicore offerings. The company blamed the severe market downturn, which has made it difficult to sell intellectual property. "IP licensing is going through a rough time right now. This is true for virtually everyone," said Dennis Kish, vice president of marketing for Actel.
"It will take a while for the market to develop. I guess you can say that it has stalled," added John East, Actel's president and chief executive officer.
One of the most obvious problems with embedded FPGAs is their poor logic density relative to ASIC gates. At the 0.18-micron technology node, 5,000 FPGA gates take up 1 square millimeter of die area-enough to fit 100,000 ASIC gates, Vasishta noted.
With the pilot projects, designers would often lean toward using more FPGAs to maximize flexibility in the end device. This turned out to be too much of a good thing. In many cases the FPGA portion would take up 30 percent or even 50 percent of the die, Vasishta said. Sudden die-size inflation can hurt wafer yield, not to mention power consumption, and wind up countering any advantages that having postproduction programmability on board can bring.
Performance of the embedded FPGA is another hang-up. Adaptive Silicon's latest FPGA core for 0.18-micron design rules has a system clock rate of 50 to 100 MHz and a maximum toggle rate of 250 MHz. LSI Logic's 0.18-micron G12 ASIC process, by contrast, runs at a 400-MHz system clock.
Some point to these yawning disparities as evidence that proponents of embedded FPGAs have taken a wrong turn. "They want to have their cake and eat it too," said Erik Cleage, senior vice president of marketing for Altera Corp. "The concept of PLD cores has been talked about for several years, and the fact that it is less probable [than initially believed] is obvious by the lack of execution of product."
Altera has had no shortage of requests to license its FPGA technology, but the company believes embedded FPGAs have too many flaws. If anything, the concept trivializes programmable logic as just another core that can be embedded into an ASIC, the company holds. "It's the programmability that is fundamentally the main value proposition," Cleage said. Forced marriage
Others point to the daunting task of combining different design methodologies when marrying FPGAs and ASICs, flows that demand different tools starting from the creation of the register-transfer-level code all the way to placement and routing. Designers effectively have to wedge the FPGA design flow into an ASIC methodology and come up with a way to partition the logic between hardwired and programmable gates.
"There's a lot of going on there that's different from the normal motion of doing an ASIC," sa id Tom Hart, president of FPGA vendor QuickLogic Corp. "You're talking about different place and route tools and different delay modeling. And it's not like a sea of gates; it's a sea of cells. You've got to use [FPGA vendor's] software to map your logic to his FPGA, and then you've got to program it." Bridged flow
Still, the incompatible design flows may not be a showstopper. LSI Logic claims it has been able to bridge those differences in its own ASIC tool flow. "We invested a lot of effort, time and money to make sure it was market-worthy. We have the capability," Vasishta said.
"We made it look and feel very much like an ASIC design vs. an FPGA design."
But Vasishta acknowledged that prospective customers found the technology too "disruptive" to take a gamble on it. "You're never going to get a flood of customers for something new," he said.
While embedded FPGAs have stalled, at least for now, alternative architectures are popping up that are somewhat less radi cal but that have many of the same goals. One company, eASIC, touts an FPGA-like cell that does without most of the interconnect of an FPGA and is mask-programmable, which provides speed and logic density closer to that of a cell-based ASIC. Meanwhile, a number of ASIC makers-including NEC, AMI Semiconductor and ChipExpress-are coming out with new silicon platforms that incorporate an array of logic cells as a way to shorten design cycles and reduce nonrecurring-engineering costs.
LSI Logic is taking a keen interest in this new breed of gate-array-like architectures.
Some say there may still be opportunity to wedge some FPGA blocks in the white spaces of chips designed at the forthcoming 90-nanometer technology node, similar to how embedded memory is inserted today.
Xilinx, too, said it is still investigating the use of embedded FPGA blocks. "I'd hate to rule it out," said Erich Goetting, vice president and general manager of Xilinx's advanced-products group. "The question is, How b ig are the application areas?"
Copyright © 2003 CMP Media, LLC | Privacy Statement