ORLANDO,Fla.Christine King, chief executive officer of AMI Semiconductor (Pocatello, Idaho), kicked off the 2002 Custom Integrated Circuits Conference with a clarion call for improved standards and design methodologies for the integration and test of intellectual property.
"This is the key problem in the industry now," said King, who worked at IBM Microelectronics' ASIC division for 23 years before taking the top job at AMIS six months ago. "The standards have to move as fast as the technology. We've got to do standards quickly, and not just talk about it.
"Look at GSM in the cellular arena," King said. "A standard can drive the technology. Third-generation phones could be an opportunity for a standard to drive a whole variety of technologies," including the widespread use of new materials such as silicon-on-insulator for low-power devices, she said.
The Virtual Socket Interchange Alliance, which is looking to set stan dards regarding intellectual property reuse, is making slow progress, King said. "It hasn't gotten real traction. People are working very hard on it, but we haven't seen the actual silicon developed along the VSIA method. When a major user adopts it and embraces it, then it will become a standard, but that hasn't happened yet and that's the main reason it is lagging."
Some companies have "open" methods that accept third-party IP, such as IBM Corp.'s CoreConnect bus, and ARM Ltd.'s Amba bus, but those efforts are tied to IBM's PowerPC and ARM's processors respectively, King said.
Block, chip and system verification
With 0.09-micron process technologies headed to market for next year, chips with 20 million gates will mandate the use of both hard and soft IP.
"IP can be pretty well verified within a block, but progress needs to be made to verify IP blocks within a design, and then verify again at the system level," she said.
"We also need IP blocks for switched fabric I/O," such as Rapid I/O, Infiniband, HyperTransport, and XAUI, that can be verified at the chip level, King said.
As digital process technologies move below 0.10 micron, a gap between digital and analog capabilities will grow. Because leading-edge digital technology is not analog friendly, a four-year gap between the application of a leading-edge process to digital functions and analog functions has emerged. The processes must support higher voltages, better isolation and thicker gate oxides in order to bring analog circuitry on-chip.
King concluded with a five-point agenda which she said would help the semiconductor industry get back on track toward growth and profits:
1.) a description language that concurrently creates RTL;
2.) at-speed system and design co-verification;
3.) totally interoperable EDA tools;
4.) high-speed I/O that works in system-on-chip designs.
5.) validated IP that works in SoC designs.
During a question-and-answer session that followed her keynote, a groundswell of opinion from analog designers arose about the problems of developing process models that are accurate enough for analog circuits. While the transistor models used to develop digital libraries can be developed fairly quickly, it takes more time and effort to create models that cover the parameters needed for analog circuits, designers said. Companies may devote 40 engineers to creating digital models, and only two for analog models, King said.
Moreover, each process at a fabrication facility, even those using the same design rules, run slightly differently when it comes to analog circuits. The 0.18-micron mixed-signal process at Taiwan Semiconductor Manufacturing Co., for example, is slightly different at the several fabs it operates.
Several CICC participants suggested that the conference with its technical "nuts and bolts" agenda and analog emphasis expand to support a discussion between analog design engineers and others dev eloping models for major semiconductor foundries.