Shakeel Jeeawoody, Blue Pearl Software
EETimes (2/19/2014 04:38 PM EST)
In this column, I'd like to introduce a novel technique for Intellectual Property (IP) and FPGA/ASIC clock domain crossing (CDC) analysis using a Grey Cell methodology rather than the traditional Black Box methodology.
The growth of IP-based design
As design complexity escalates, designers increasingly rely on commercial or existing IPs to meet project deadlines rather than designing everything from scratch. According to Semico Research, over the next couple of years, the number of IPs per design will increase from an average of 50 to a staggering 180.
The difficulty of IP integration and design verification will undoubtedly grow exponentially. Even today, many design teams complain that it takes too long for integration and verification using existing methodologies. Just imagine the resulting dreadful situations as the number of IPs per design goes up. To alleviate these types of issues, EDA vendors need to provide breakthrough methodologies. Previously, Blue Pearl Software introduced the Grey Cell methodology, which was discussed at DAC 2012 and elaborated on in EETimes.
With the recently introduced User Grey Cell methodology, Blue Pearl enables IP providers and FPGA designers to reduce the risk of missing CDC issues. In this paper, we illustrate how the recently introduced patent-pending User Grey Cell methodology reduces metastability.
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