Yield-raising methodology closes loop between design, manufacturing

Yield-raising methodology closes loop between design, manufacturing
By Thomas Martis, EE Times
March 17, 2003 (3:38 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030317S0045

With semiconductor companies increasingly adopting the fabless model, there is a lack of postdesign "product development" methodology. After tapeout, companies perform little or no characterization of the actual devices. In the absence of characterization, little can be done to improve yields.

When a company does characterize, the sheer quantity of data and lack of analytical tools limit feedback to a manual comparison between specifications provided by the design engineer and real product data collected by the product engineer. That comparison typically determines whether the performance of the product meets design specifications across process variations, and if so, at what yields.

For example, designers responsible for output buffers typically perform four-corner simulations (FAST, FAST-SLOW, SLOW-FAST and SLOW) using models that comprehend process control monitors (PCMs) and metrology/process information. This gives them rise and fal l times of output signals at each corner.

When a characterization methodology exists, the product engineer will initiate the manufacture of three to five skew lots along the boundaries specified by the foundry. During that manufacture, the foundry collects PCMs for each wafer. The wafers are then diced and packaged, and the product engineer runs test vectors at different operating conditions on each part. More often than not, at least one spec will not be met or will have marginal yields.

To fix the problem, engineers often resort to speculation. They look at the output of the real component and compare it with their simulations. They then modify their design as best they can to account for difference between the real and simulated data.

A better course would be to determine relationships between the PCM parameters and the outputs of the actual component by correlating the two. Concurrently, additional simulations should be run that incorporate the PCM data gathered during the skew-lo t manufacturing and the process information used to manufacture the lots. A sensitivity model then can be developed to represent the difference between real and simulated, and the design can be modified to get the desired results to a higher level of accuracy.

Numerous simulations should be run covering cases representing the process settings and the PCM parameters for the skew lots. Next, the data obtained from the characterization of the skew lots needs to be condensed into transfer functions that explain the relationship between PCM parameters, skew-lot settings and the output of each skew part. Finally, a sensitivity model needs to be developed between simulated and actual by correlating the simulation results to the characterization data.

All of this can be accomplished either manually or with tools that automatically generate the necessary transfer functions and then correlate them to the simulation data.

Following this methodology is akin to closing the loop in a control syste m. It can help get products into volume manufacturing with the highest yields and fewest design turns possible.

Thomas Martis is CEO of Siverion (Tempe, Ariz.), a provider of engineering data analysis software.

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