SoC Embedded Memories: Overview
By Chappell Brown , EE Times
April 28, 2003 (3:55 p.m. EST)
Memory system design has been a preoccupation from the computer's very earliest days . Many approaches have been tried, and some of them-static RAM, ROM, DRAM and magnetic-disk storage-have a very long history. Now the system-on-chip generation needs to address these complex solutions for the storage of digital data in the context of total on-chip integration.
A pivotal function in the past, memory subsystems are shaping up as even more significant for SoC technology. Solicited by our SoC process editor, David Lammers, articles in this week's In Focus look into exactly what it takes to embed memories at these dimensions.
The Semiconductor Industry Association calculates that embedded ROM, RAM or register file memories of various sizes consume up to 50 percent of the die area of most system-on-chip designs, a figure the SIA sees increasing to 71 percent by 2005. "The SIA and ITRS [International Technology Roadmap for Semicond uctors] have estimated that by the year 2014 embedded memory will account for over 90 percent of the area on a chip," Jay Abraham, product-marketing manager at Silicon Metrics, observes in his contribution.
But adding a memory component to a system-on-chip means finding a well-tested, well-characterized block of intellectual property (IP) that can drop into a complex circuit design. Engineer Frank Ramsay of Toshiba America Electronic Components' System LSI Group observes in his article that the two mainstays of semiconductor memory-DRAM and SRAM-are becoming highly significant components of SoC designs.
"Improvements in DRAM manufacturability have caused a boom in the use of large DRAM blocks. Even ASICs for commodity products such as game machines and camcorders include DRAM cores," Ramsay says. It is common to find a design using 64 Mbits of DRAM, and leading-edge 90-nanometer chips may have 120 Mbits on board.
The market for memory IP promises to be large, since most pr oject managers want to concentrate the engineering expertise of their designers on what is unique about the product, not on the memory. As in the past, the ideal situation is to simply drop in a standard memory component where it is needed, Krishna Balachandran, senior director of product marketing at Virage Logic Corp., observes in his piece.
Meanwhile, several exclusive online contributors look at both the design-level issues of IP reuse and the bottom-up issues of building various memory types into a single, manufacturable chip.
One evolving area is multiport memories. Bill Beane, strategic marketing manager at IDT, points out in his piece that "in the coming years multiport memory designers will continue to drive down power consumption by reducing core voltage to 1.8 volt and below." He notes that at the same time, "the migration to newer semiconductor process technologies with smaller internal geometries will allow architects to aggressively increase multiport memory densities to support rising data traffic rates and escalating buffering requirements."
Synopsys' Mick Posner discusses how existing HDL based embedded memory model simulation capabilities fall far short of today's verification requirements. And Bret Siarkowski, director of strategic technology at Verplex Systems, offers his perspective on how memory is overwhelming current verification techniques. A solution may be found in an integrated approach combining parameterized RTL memory models, automatic transistor abstraction, equivalence checking and system-level model generation.