Co-design or bust: SoC FBGA packaging
Co-design or bust: SoC FBGA packaging
Co-design or bust: SoC FBGA packaging
By Gary P. Morrison, Package Development, Vinu Yamunan, Flip Chip Packaging Engineer, Adelina Gonzalez Lewis, Flip-Chip Packaging Engineer, Texas Instruments, Dallas, TX, email@example.com, EE Times
May 23, 2003 (9:51 a.m. EST)
SoC designs require the integration of digital signal processor cores, custom logic, memory and analog on a single chip. Consequently, these designs require signal integrity of critical nets, and adequate power distribution in both the chip and the package. And, these designs present a formidable challenge more so when packaged in high-speed, low-cost, flip Chip Ball Grid Array (FCBGA) substrates.
FCBGAs have been around for close to 40 years. They are used predominantly in high IO count applications, such as microprocessors and custom ASICs that support the higher cost of the package. In the last 10 years, though, costs have decreased to the point where FCBGAs are used in many applications, including high performance DSPs.
Nowadays, FCBGAs are usually chosen over wire-bond packages to provide tighter IR drop budgets, lower inductive parasitics, better signal integrity and greater silicon entitlement.
The integration of FCBGAs with SoCs has to be made without sacrificing performance, cost or cycle time. This challenge demands a shift from traditional package design methods and tools to a systems design approach package co-design.
The typical SoC package designer wrestles with many new challenges compared to the previous generation of IC package designs. To name a few:
-comprehending the interaction and IO planning of multiple functions on a single chip and package,
-handling of an order of magnitude more design data,
-minor tweaks in the IC or package design can lead to more design work,
-tighter integration of chip IO planning, system-level reliability and manufacturability testing, as well as system-level electrical, thermal and mechanical modeling,
-and then there is the steep learning curve for new, more powerful package design tools.
Since design changes originate from many different functional areas, usually beyond the control of the package designe r, they usually end up being applied piecemeal. To help stave off this piecemeal approach and associated difficulties, SoC designers can borrow some methods and tools from modern systems design.
One way to reduce iterations is to use "look-ahead" test and modeling vehicles. These support system-level reliability and manufacturability testing, and system-level electrical and thermal modeling.
Look-ahead vehicles come in two forms: an actual mechanical model for reliability and manufacturability testing and a paper schematic for feasibility and electrical modeling analysis.
Package designers need to follow a certain amount of discipline and commitment to use these vehicles. But once part of the standard co-design flow, they allow new product teams to get ahead of demands and deadlines in package design and analysis, despite all the changes complex designs require. This approach helps answer general design questions early in the process, and at a fraction of production test costs. p>
Custom automation tools, such as EDA, provide fast and efficient communication and verification of data between different design environments. They provide SoC package designers with powerful design and routing capabilities, built-in checks, standards and reporting features, such as design rule checks (DRC), standard netlist syntax, and connectivity reports.
Spreadsheets are a common platform for these automation tools since they are available in almost all design environments and easily scale to handle large volumes of data. This type of automation reduces the time spent manipulating relatively large datasets. Consequently, these tools help designers avoid manual errors when working with large amounts of raw data.
The right mix
The development of package co-design methods and tools is ongoing. Although we not might not be to the point that we have comprehensive, user-friendly, and tightly integrated tools that seamlessly span all design environments, existing package c o-design tools, with the right methodology and custom-developed internal tools, will provide crucial benefits.
These tools have allowed advanced package designers to meet essential SoC performance requirements, reduce advanced package costs, and cut design cycle time in half and verification time from days to hours. Some examples:
-Case 1: An SoC designed for broadband network applications included multiple DSP cores, custom logic, memory and ASIC macro cells on a single piece of silicon. The components were assembled onto a multiple-layer, high-density substrate, and required isolated power planes and strict signal integrity standards. These requirements led to diverse shielding schemes edgewise and using a ground plane.
As part of the "electrical look-ahead test vehicle" an estimated substrate design was created as artwork. The physical substrate was not manufactured for empirical measurements. This substrate design was used for 3D electrical modeling, simulation, and va lidation performed with proprietary and third-party software tools. The experiments included different assignment schemes of nets to BGAs and their impact on the electrical performance (signal integrity). This process was instrumental in evaluating and comparing BGA assignment and artwork design schemes early in the project. The process also helped compare package performance strengths and weaknesses with product requirements.
In several cases, optimization of the substrate layout (BGA assignment and/or routing artwork) led to modification of the flip chip bumps' net assignments. This would have been next to impossible with conventional package design (before "co-design"), which traditionally starts late in the project. Within the co-design paradigm, optimization is possible and quite feasible early in the process.
-Case 2: A PCI (Peripheral Component Interconnect) card bus p roduct required multiple power supplies and separate grounds for digital and analog/RF. Part of the package substrate co-design effort required an understanding of the die floor plan so that the layout of these power and ground planes could adequately support the SoC. Additionally, the analog and RF portion of the die needed to be isolated from the digital noise and vice-versa.
The package designer decided on an FCBGA with a multiple-layer substrate. One layer of the package substrate was dedicated to ground. That layer was bisected to support two separate ground planes. Likewise, another layer of the package substrate was dedicated to power. That layer was partitioned into multiple sections to support the power planes. The power planes were extended from the die area to the edge of the package. This allowed the signal balls to be contained within the area of their power plane.
The configuration of the substrate's power and ground layers provided shielding to each group of signals with the correct power supply and ground. Critical signals and differential pairs were shielded with ground balls and wide ground traces. The critical signals were simulated to check for interference from adjacent signals and adjacent power supplies.
We believe that a chip-package co-design methodology is essential for effective SoC FCBGA packaging. The alternative to a system package co-design approach could fall well short of the goals of higher performance, lower cost, and faster cycle time.
The failure to identify and meet the essential system-level requirements, or to not apply lessons-learned, can lead to disappointing performance. Similarly, the lack of processes to quantify the design trade-offs, and to perform critical system-level analysis, can increase design costs. Finally, incomplete feasibility studies and failure to capture key interactions at the system level can result in unexpected package redesigns.
The net result is a device late to market and with expensive, ove rly conservative packaging that can knock a breakthrough product to its knees.
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