ANAHEIM, Calif. Steve Sutton, vice president for ASICs at Texas Instruments Inc. looked across the DAC press room, but his eyes were focused on a broader reality. It is a very different industry than last time the Dallas-based semiconductor giant put an external emphasis on the ASIC business.
''There's really two segments in our end of the ASIC market,'' Sutton said. ''There's the telecom infrastructure business and the rest of the world. Infrastructure design starts are down incredibly. But if you look away from that, at enterprise telecom, networking or the non-communications markets like consumer and automotive, they are not slowing down that much.''
Sutton admitted that this wasn't the impression given by the numbers. ''It's not obvious,'' he said. ''The total number of design starts is down, for a couple of reasons. But the value per design start is actually up.''
He said two factors were driving the reduction in design starts in the surviving part of the industry. First is integration. Systems vendors are sharply reducing the total number of packages in their system designswhere there might have been four ASICs last year, now there will be one highly integrated chip. That leads to a sharp reduction in design starts.
A less obvious factor, according to Sutton, is that large companies are for the first time becoming strategic, planning ASIC design starts on a company-wide basis.
''A company will look at the ASIC requirements across all their divisions,'' Sutton explained. ''And where they see commonality, they'll say, 'Look, guys. The chip you want to do is a lot like the one we need over here. Why don't you get together with these guys, and those guys, and this team over here, and do a single design that will meet all the needs?'"
That approach "gives them a high level of not just IP reuse, but design reuse, and amortizes the design costs,'' Sutton said.
The move toward the formation of platform designs is deve loping spontaneously within large organizations, and is also accelerating across company boundaries. Sutton also said that many design teams have stepped off of the old Moore's Law treadmill. ''We have a 90 nm process up, and we have produced cell phone chips in it,'' Sutton affirmed. ''But we don't see anyone going to 90 nm unless performance requirements are driving them there. Most of the activity is designs moving to higher levels of integration at 130 nm."
The process of winning a design start has also changed, according to Sutton. Until the downturn, ASIC vendors could compete on process technology and roadmaps. But with many design teams hesitant to move to advanced process nodesoften frightened by horror stories from the pioneers at 130 nmprocess appears to be less a differentiator.
''The way you win in some of these markets is to lead with IP,'' Sutton said. ''A proprietary processor or DSP core is obviously a lock-in. But so is a serializer-deserializer if you can show silicon, show a record of first-pass success and demonstrate interoperability across the customer's backplane. We've spent two hard years learning to do that.''
The designs are there to be had, Sutton suggested. But there are fewer, and they are more demanding in terms of integration. They will also demand competition on the performance of individual pieces of key IP, and the ability to broaden a single highly integrated ASIC design into a platform strategy that will reduce the total number of starts for the customer. It's a different world.