A perfect storm of forces-mobility, process technology and system-on-chip complexity-are combining to create a tsunami of challenges for SoC designers who need to manage dynamic power consumption and static leakage at 130- and 90-nm process technologies.
At 130 nm and 90 nm physics begins to work against the designer in regard to power. In previous technology generations, just moving to the lower geometry produced a significant power reduction. Going from 0.25 micron to 0.18 micron lowered the voltage from 2.5 to 1.8 volts, a drop of 0.7 volts. This factor alone could make up for a host of power problems. But future technologies will have voltage levels hovering consistently around 1.2 to 1.0 volts. Changing to a newer technology will provide little benefit to the power budget. Also at 130 and 90, the static or quiescent leakage becomes larger. Thinner gate oxides deliver the speed, but they do so at the price of increased leakage currents. For the foreseeable future process technology will not provide a meaningful solution to the challenge facing power.
While voltage levels maybe stabilizing the complexity of the designs is not. Designs continue to increase in size and functionality. Enabled by finer geometries, designers can double the size of their SoCs and at the same time increase the speeds at which they operate. But as we have seen, these larger, more complex SoCs are operating at the same, or roughly the same, voltage levels as in their prior-generation designs. Something has to give in the power budget.
Mobility in electronics in both consumer and business applications is a growing wave in our industry. From Wi-Fi-enabled laptops and PDAs to MP3 players and digital video and still photography, our electronic gadgets for work and play are increasingly running on battery power. While battery technology has advanced significantly, producing smaller and lighter batteries with great operating life, the problem of power must be fundamental ly answered within the chips themselves.
Power islands are segregated, contiguous portions of a chip, isolated from the rest of the chip in terms of voltage and frequency. By creating voltage- and frequency-independent islands, the designer has the option to manage the voltage level and clock frequency for optimal power consumption and leakage performance. These islands can even be shut off completely when not in use. Power islands allow designers to use many of the same power management techniques they used when these blocks were not incorporated into a single chip, but were many discrete chips that could be easily powered up and down or sped up or slowed down.
By reducing the frequency from 200 MHz to 100 MHz a 2x power savings in recognized. But further reducing voltage from 1.2 V to 0.9 V, achieves an additional 2x power reduction. The result: dynamic power consumption is reduced to a mere 25 percent of the original value.
Power islands have been used successfully in advanced microprocessor d esign (Intel X-scale and Transmeta Crusoe) and for a few extremely high-volume consumer applications like cell phones. But until now the technique of creating and managing power islands has been largely ad hoc, custom-designed and labor-intensive. As a result it has been available only to these very few high-volume applications. Implementing power islands meant developing custom circuit-level IP and unique design flows, not support by existing EDA tools. That investment could be made only by a very few large design teams with significant internal resources in circuit design and modeling, and the high-volume application to justify the expense. The rest of the world was left out-and left holding extra batteries and heat sinks.
Virtual Silicon has introduced the first commercially available standard-cell library to enable creation and management of power islands. The VIP PowerSaver library includes a unique set of cells to perform the voltage level shifting and voltage isolation required to construct power islands and open up new power management options for the SoC designer. The library also includes a set of clock gating cells and ultralow-power flip-flops, producing 30 percent lower power than standard flip-flops and resulting in more than 700 cells.
While power-management enabling IP is the critical first step, a number of other elements in the design flow need to be enhanced. Many power analysis EDA tools can handle multiple voltage levels. But synthesis tools and construct tools cannot deal with mixed voltage levels in an automated manner. But some product announcement is expected to be made before this June's Design Automation Conference.
At 130 nm and 90 nm, SoC designers will have no choice but to use power islands to manage increasingly severe dynamic power and leakage current issues. By enabling designers to lower and raise the voltage and frequency of individual power islands, designers can significantly lower both the dynamic power and the quiescent, or leakage power of their designs. Vir tual Silicon will be making the enabling IP technology available to the majority of designers in the market, many of them without the resources to develop the required IP in-house.
Barry Hoberman is president and chief executive officer of Virtual Silicon (Sunnyvale, Calif.)
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