SoC IP Blocks Solve the 3G Power Management Issues

At 130 and 90 nanometers, power consumption, both dynamic and static, is a major hurdle to overcome in the development of system-on-chip designs for third-generation (3G) cellular handsets and other battery-powered mobile applications. The fundamental designs of mobile phones (GSM, GPRS, CDMA and so on) are increasingly complicated by multiple wireless technologies including 802.11, Bluetooth, GPS, ultrawideband and even TV. Add larger color screens and the growth of new applications for phones including security, audio, imaging and online gaming, and the design task enlarges rapidly.

Analog Devices Inc. reports that in today's GSM cell phones these functions account for 95 percent of the current consumption in talk mode and 29 percent of the current consumption in standby mode. These percentages will only increase in 3G phones, resulting in greater and greater energy demands placed on the battery. Since no one wants a larger, heavier cell phone to accommodate a larger battery, power must be reduced.

All of this is happening just as the physics of the silicon at 130 nm and, especially, 90 nm (particularly in the power part of the equation) start to work against the engineer. As voltage levels stabilize around 1.2 and 1 V, there is no automatic reduction in dynamic power when you move from 130 to 90 nm.

But even more critical is the increase in leakage current. Thinner gate oxides and lower threshold voltages (0.6 V) result in a significant increase in leakage current and static power consumption. There are, in total, seven additional secondary sources of leakage current, all of which get worse at 130 nm and even more so at 90 and 70 nm.

Foundries and independent device manufacturers' internal wafer fabs address power through several process variations at 130 and 90 nm, each optimized for speed, power or low voltage. The only thing these processes really offer designers, however, is the classic power/speed trade-off. They can have a high-speed, high-leakage process or a low-speed, low-leakage process.

The process performance operates on the fundamental physics of the semiconductor. By raising the voltage threshold of the transistors, the leakage can be reduced, but this comes at a corresponding decrease in the speed of the transistor. Low-power or low-leakage processes have unacceptable performance for 3G applications.

Low-power intellectual property (IP) is often touted as the solution. But again, all that is really offered to the designer is the same classic power/speed trade-off as at the foundries. Savings in power are achieved through the use of higher-threshold transistors and by designing circuits for reduced power, but both methods come with a harsh speed and area penalty.

For low-speed applications, such as today's cell phones, this technique produced acceptable results. The faster speed of the 180 nm process tends to offset the loss of performance of the low-power IP. But for 3G wireless products at 130 nm with greater graphics and video capabilities and with high speed wireless Internet connections, the performance trade-offs are unacceptable. Power must be saved, but not at the sacrifice of performance.

Power-management IP

With the physics of the semiconductor working against the designer at nanometer process technologies, the designer must turn to the voltage and the clock frequency of the system-on-chip (SoC) to find power savings. In the simplest sense, designers want to be able to treat individual blocks of an SoC in much the same way they did when those parts were separate chips on a printed-circuit board. These chips could run at different clock rates and different voltages and could be turned off when not in use in order to save power.

The designer needs to be able to partition the SoC into electrically autonomous areas, called power islands, based on functionality (CPU, MPEG-4, memory, analog and so on) and power requirements, and then be able to dynamically scale the voltage and clock frequency of the power islands so that each island is running only at the performance required at that time. This allows the designer to lower the voltage levels and clock speeds when high performance is not required and, as a result, save power. By dynamically managing the voltage and frequency of individual power islands, designers can significantly lower both the dynamic and the quiescent or leakage power of their SoC designs.

Dynamic voltage and frequency scaling can be added to many of the other current power-optimization techniques. However, full implementation of this technique requires a vertically integrated approach within the SoC design supply chain. It also requires power-management IP. More than just low-power IP, this technology allows the designer to actively control and manage the power consumption of the SoC during operation. The CPU and software can issue commands to dynamically scale the voltage, frequency and leakage current of the power islands of an SoC. That allows the designer to leverage the enabling elements of the SoC design supply chain — low-power IP (standard cells, memory, etc.), software, SoC IP (CPU, DSP, etc.), process technology and power supply IC — to dynamically manage the power of an SoC while it is operating.

The first step is in the foundation IP, which will enable the construction of power islands, and in the EDA tools with which to implement the design. The first commercially available library that enables the implementation of power islands in SoCs hit the market in January. Included in the library are voltage isolation cells, voltage level-shifting cells and couplers.

All of the cells are characterized at 1.2, 1 and 0.8 V to facilitate designing at mixed voltage levels. Using the standard cells, designers can create SoCs with any number of power islands, each of which can be independently powered on and off, or have the voltage level and clock frequency dynamically changed.

The power islands created using the power island-enabling library can contain logic and memory or any kind of other third-party IP including RISC or DSP cores, analog cores or other hard or soft macros. The SoC could be implemented with standard IP, low-power IP or both — it doesn't matter.

Software needed

Now that these key enabling hardware technologies are available, the designer needs power-management software that can issue instructions on when to scale the voltage and frequency for optimum power consumption. ARM's Intelligent Energy Management (IEM) software is one of the first offerings on the market.

The IEM software consists of sophisticated algorithms working together with the embedded power-management IP. The IEM software interacts with the operating system and application software to predict processor loads and determine the required performance level, and scale the voltage and frequency accordingly.

While the power crisis in nanometer SoC design is clearly a challenge, designers are beginning to see the integration of a new breed of power-management IP with other elements of the design supply chain. In the coming months and years, additional innovative products will deliver into the hands of the designer even more powerful weapons in the battle with nanometer power.

John A. Ford (johnf@virtual-silicon.com) is the vice president of marketing at Virtual Silicon (Sunnyvale, Calif.).

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