Many products and methodologies are available for block-level verification, but system-on-chip (SoC) interconnect analysis is not so well served. At a recorded Cadence Theater presentation at the 2013 Design Automation Conference, Ravi Kalyanaraman, Verification Manager at Marvell Technology Group, spoke about his company's experience with interconnect analysis and discussed what he feels is needed.
Ravi first noted two key challenges that Marvell sees in SoC integration validation. One is incorrect handshake assumptions between IP blocks. Another is incorrect interconnect configurations, a problem that can severely affect system performance and may not be discovered until late in the design cycle.
Traditionally, Ravi said, integration validation has consisted of stitching IP blocks together and running a limited set of tests to find the "low hanging fruits" in terms of bugs. While this has been acceptable in the past, running a limited number of basic tests increases the risk of finding bugs late in the design cycle. "The limited time between bring-up and tapeout hardly gives any time for doing a thorough interconnect verification," he noted.
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