Industry Expert Blogs

As Moore’s law slows, engineering ingenuity has created innovative ways to push the boundaries of physics. Multi-die chip designs, whose heterogeneous integration of semiconductor dies enable better bandwidth, performance, and yield, have emerged from this. In addition to packaging advancements, what has also made multi-die chip designs possible is the Universal Chiplet Interconnect Express (UCIe) standard for die-to-die connectivity.

By mixing and matching dies, or chiplets, from different vendors and even foundry process nodes, chip designers gain the flexibility to target particular dies to particular functions. Not all functions need to be on the most advanced nodes, so designers can potentially capture some cost savings while attaining an easier way to adapt their chip designs for different product variants. UCIe IP standardizes die-to-die connectivity and enables disparate dies to talk to each other.

What’s more, sourcing IP from a single vendor allows you to take advantage of a complete chip design and verification flow with IP for a variety of process technologies (even if the dies in your design come from multiple vendors and foundry process nodes). Other benefits of this approach include:

• Reduced design time and risk
• Enhanced quality of results
• Faster time to results

Synopsys, which provides a broad UCIe IP solution optimized for the major foundries and for standard and advanced packaging, has witnessed how these benefits can be realized across the major foundries. Read on to learn more about the gains of mixing and matching dies in a single package and how UCIe IP from a single vendor supporting multiple foundries and multiple nodes can lead you to silicon success.

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