Industry Expert Blogs

For today’s mobile and high-performance systems, low-power design is essential. Such designs are more sustainable, translate to longer battery life, create better seamless consumer experiences, and reduce energy costs. All these benefits aside, reducing power consumption is a challenging task for chip designers and verification/RTL engineers. Next-generation SoCs are expected to be 10x larger, and low-power signoff for some designs can take as long as a couple of days. Clearly, an advanced low-power verification solution is needed to help engineers validate complex low-power structures within a reasonable turnaround time.

One such solution is Synopsys VC LP™ Advanced static low-power verification solution, which has successfully passed Samsung Foundry’s certification process. As a static checking product, VC LP Advanced technology effectively addresses the complexity of validating low-power designs, streamlining and expediting the debugging process.

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