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ARC International Provides New Configurable Trace and Debug Extensions to the ARC 600 and 700 Core FamiliesNew Extensions Reduce Transistor Count by More Than 90 Percent and Enable Hardware/Software Co-Design Efficiency ELSTREE, England, November 29, 2005 – ARC International plc (LSE: ARK) the world leader in configurable CPU/DSP processor cores and application subsystems, today announced the availability of new configurable trace and debug extensions for the ARC™ 600 and 700 core families. The new extensions only add 5K gates of logic compared with more than 100K from alternative offerings,.and are seamlessly integrated into ARC’s MetaWare™ integrated development environment and the ARChitect™ processor configurator. ARC carefully analyzed user requirements for software debug in real-time systems and selected the most efficient features to produce a solution which is small enough to be realistically implemented in the final chip. “ARC’s new debug and trace extensions are another way in which we are lowering the cost of SoC design using our patented configurable technology,” said Peter Hutton, senior vice president of engineering for ARC International. “The extensions are small enough to allow developers who need to increase their software debug productivity to hit tight time to market windows to put them on the final chip, without killing their equally critical area and power budgets.” About ARC’s New Debug and Trace Extensions ARC’s new debug and trace extensions are an on-chip debug hardware module that SoC designers can add to an ARC 610D, 625D, 710D, 725D or 750D core using the ARChitect processor configurator. They increase core logic only by 5k gates and provide powerful software development capabilities that rival in-circuit emulators. With the debug and trace logic embedded within the CPU core, software designers have visibility into the operation of their software execution. During trace, the debug module stores the address of any non-contiguous instruction being executed. Thus, a designer can examine the machine state before and after a software or hardware breakpoint. Repeating loops are identified by the LSB (least significant bit) of the flow-change source and destination addresses. The MetaWare debugger enables the logic and displays the instruction trace history. It will read the saved instruction trace information via the JTAG port when the processor is halted using the system clock, which will be gated when tracing is disabled. All inputs to the debug logic will be zeroed when not in trace mode to provide additional power savings. ARC’s new extensions run at the full speed of the cores within the 600 and 700 families. Availability ARC’s real-time trace and debug extensions are available in Q1 and come as standard components within the ARChitect processor configurator. About ARC International plc ARC International is the world leader in low-power, high-performance 32-bit configurable CPU/DSP processor cores, subsystems, real-time operating systems and development tools for embedded system design. ARC’s patented configurable CPU technology assists customers in the development of next generation digital media, consumer and communications devices, resulting in lower cost, higher performance SoC products. ARC International maintains a worldwide presence with corporate offices in San Jose, California, USA and Elstree, UK. The company has research and development offices located in England and the United States. For more information please visit the ARC website at: www.ARC.com. ARC International is listed on the London Stock Exchange as ARC International plc (LSE: ARK).
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