Time for Structured ASIC?
August 07, 2007
Introduced a few years ago as a cheaper replacement to FPGA, Structured ASIC looked for a while as a quick success story for fabless semiconductors manufactures. In fact Altera found it necessary to come out with its own line of structured ASIC devices derived from its Stratix FPGA line just to make sure they would not loose designs initially implemented in FPGA to another manufacturer when the customer achieved volume production.
In fact the segment grew much slower than anticipated and a few startups looking for fame and fortune in this market quickly disappeared. But as development costs and design risks increase at leading edge process nodes, designers are looking for any method or tool that will allow them to meet requirements, schedule, and cost targets. And so, structured ASIC are gaining interest as an implementation alternative.
E-mail This Article | Printer-Friendly Page |
Related News
- Faraday Offers Peripheral Composer, the Fastest Time-to-Market Structured ASIC for Peripheral Interface Chips
- Sondrel creates unique modelling flow software to cut ASIC modelling time from months to a few days
- First Intel Structured ASIC for 5G, AI, Cloud and Edge Announced
- Is It Time to Forget about Huawei?
- Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process