Digital Blocks Expands Video Signal & Image Processing IP Core Family
The Digital Blocks new Video Signal & Image Processing IP Cores include a Color Space Converter, Chroma Resampler, CCIR BT.656 Encoder & Decoder, and system-level IP for RGB-to-CCIR 601/656 conversion.
GLEN ROCK, New Jersey, January 31, 2012 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with Embedded Processor & Peripherals, Networking, Display Controller, Display Link Layer, 2D Graphics, and Audio / Video processing requirements, today announces six IP Core additions to the Video Signal & Image Processing family.
Digital Blocks’ Video Signal & Image Processing IP Core Family includes the following:
DB1800 - Standard Definition NTSC/PAL/SECAM Video Sync Separator
Digital Blocks DB1800 Video Sync Separator IP Core extracts timing information from a standard NTSC/PAL/SECAM composite sync video signal, extracting horizontal sync, vertical sync, chroma burst / back porch, and field 1 (odd) or field 2 (even) detection.
DB1810 - Color Space Converter
Digital Blocks DB1810 Color Space Converter IP Core transforms three color components between 10+ color spaces.
DB1820 - Chroma Resampler
Digital Blocks DB1820 Chroma Resampler IP Core down converts 4:4:4 Y’CbCr to 4:2:2 Y’CbCr in accordance with the ITU-R BT.601 standard requirements. Includes image rejection filter.
DB1825 - RGB to Y’CbCr Color Space Convert with 4:4:4 to 4:2:2 Chroma Resampler
Digital Blocks DB1825 Color Space Converter & Chroma Resampler IP Core transforms 4:4:4 sampled RGB color components to 4:4:4 Y’CbCr color space followed by Chroma Resampling to 4:2:2 Y’CbCr color components (combined DB1810 and DB1820 products).
DB1830 - BT.656 Encoder
Digital Blocks DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC & PAL video ITU-R BT.656 digital coding standard.
DB1840 - BT.656 Decoder
Digital Blocks DB1840 CCIR 656 Decoder IP Core decodes a ITU-R BT.656 digital framed signal into 4:2:2 Y’CbCr component digital video with synchronization signals.
DB1892 - RGB to CCIR601/656 Encoder
Digital Blocks DB1892 RGB to CCIR 601 / CCIR 656 Encoder IP Core interfaces RGB data along with synchronization signals from a LCD Controller (such as Digital Blocks’DB9000IP, or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.
Price and Availability
The Video Signal & Image Processing IP Core Family is available immediately in synthesizable Verilog along with synthesis scripts, a simulation test bench with expected results, installation guide, and a technical user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA).
|
Digital Blocks Hot IP
Related News
- Chips&Media announced Image Signal Processing (ISP) IP family targeting surveillance and automotive products
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
- CAST Introduces 8K Video Codecs and Advanced Image Signal Processing IP Cores
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with targeted applications in DMA Streaming of Video and Data over PCIe or UDP/IP Network Interface.
- intoPIX TICO-RAW technology to simplify and improve image signal processing of next-gen 4K & 8K cameras at NAB Show 2019
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |