Tabula and Algo-Logic Collaborate to Release Second Generation Ternary Search Engine

Combination of Algo-Logic’s TSE2 and Tabula’s ABAX®2P1 enables 600 million searches per second to process up to 400 Gbps of Ethernet packets in a single programmable device

SANTA CLARA, Calif., July 2, 2013 – Tabula Inc., advancing high-performance programmable logic solutions for network infrastructure systems, announced today the availability of the latest addition to its suite of high-performance packet processing solutions: the second generation Ternary Search Engine (TSE2) soft IP cores.

This series of soft IP cores was developed by Algo-Logic for Tabula’s Spacetime® architecture and is supported by Tabula’s Stylus compiler version 2.7.

Combined with Tabula’s ABAX®2P1 device, the TSE2 core performs high-speed packet classification for customized search of Ethernet IPv4 and IPv6 packets. The core implements search functions critical to equipment such as firewalls, routers, flow controllers, VOIP management systems, L2 to L7 content matching engines, load balancers and software-defined networks (SDN).

"The combination of Algo-Logic’s highly scalable, customizable, small-footprint algorithmic search engines and Tabula’s ABAX2 P-Series devices’ multi-port memories enables wire-speed packet classification for multiple 100 Gbps streams. The integration of Algo-Logic’s cores on a 3PLD device is unique and provides an ideal way to implement Gateware Defined Networking® features for wire-speed flow matching and programmable content matching in data centers.” said John Lockwood, CEO of Algo-Logic Systems, Inc.

More about the TSE2

The high-performance, customizable TSE2 matches header and payload data at 100 Gbps line rates with low, deterministic latency. Key performance metrics are:

• 150 million searches per second (MSPS) per core, scalable to 600 MSPS with four engines per device
• Large key-size widths of up to 640 bits (suitable for high N-tuple matching as described in the OpenFlow specification)
• Comparable to a legacy CAM capacity of 120 Mb (on-chip) to 7.6 Gb (with off-chip DDR3 memory), enabling usage in routers, switches, and network appliances
• Table sizes ranging from 512 fully associative to 12M exact flow match entries using DDR3 memory
• Low table lookup -latency of 256 ns with on-chip memory, and 450 ns with hybrid (on-chip plus DDR3) memory

The TSE2 is composed of two 150 MSPS soft IP cores: associative ternary search engine (ATSE2), and exact match search engine (EMSE2).  Both cores are highly flexible and achieve 100G search rates in a small footprint. 

The cores delivered in this release provide:

EMSE2 

• Configurable key sizes:  80 to 640 bits
• Up to 192K entry, 120 Mb lookup table using on-chip memory only

  ATSE2

• Configurable key and mask size:  48 to 640 bits
• Up to 32K entry table depth
• Up to 10.5 Mbit TCAM equivalent table size
• Supports unrestricted patterns and prioritized rules

Availability

The ATSE2 and EMSE2 soft IP cores for use with Stylus compiler version 2.7 are available on Tabula’s customer portal at customer.Tabula.com.   

About Tabula

Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs), based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com

About Algo-Logic Systems
Algo-Logic Systems, Inc. is the recognized leader in Gateware Defined Networking and provides gateware for Field Programmable Gate Array (FPGA) and 3D programmable logic devices (3PLD) used for advanced packet processing in datacenters, low-power mobile systems, and low-latency finance. Algo-Logic has extensive experience building IP cores that are used in wire-speed, programmable Internet routers, data center switches, and customized network processing systems.

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