BEAVERTON, Ore. -- July 17, 20133 -- Open Core Protocol International Partnership (OCP-IP) announced the availability of a white paper discussing the profiling of the Embedded Microprocessor Benchmark Consortiums (EEMBC) MultiBench Benchmark Suite in a 64 Core Machine.
The project executed 16 parallel benchmark workloads on an M5 simulator. The simulated platform contains 64 dual-issue cores with 16+16KB private L1 caches and distributed 16x1MB L2 cache, running at 2 GHz. The L1-L2 bus runs at 1GHz and is 64 Bytes wide. The measured parameters included application performance as instruction-per-cycle (IPC), traffic on L1-L2 bus, and L1 cache-miss penalties. The simulation described in the paper was limited to 1 second of application runtime because of time constraints. Measurements varied both the number of parallel workloads and worker threads per workload, in the range 1-64. Hence, the total number of threads varies from 1 to 4096 and the performance peak occurs when there are as many threads as cores, i.e. 64.
“Parallel execution is a key approach to improve system performance since the CPU clock frequencies are not increasing notably today, but, parallelism also brings challenges in communication, both at the software and hardware level”
Markus Levy, founder and president, EEMBC
Running parallel workloads achieves higher performance than using multiple workers for a small number of concurrent workloads. The measured IPC varied in the range 0.2- 6.8 and bandwidth 0.9-49 GByte/s. The average IPC was surprisingly low, only about 2 instructions per cycle, whereas the average bandwidth in L1-L2 bus was 9.2 GByte/s.
The effort was led by the Electrical and Computer Engineering Department, Boston University and the Department of Pervasive Computing at the Tampere University of Technology.
Parallel execution is a key approach to improve system performance since the CPU clock frequencies are not increasing notably today, but, parallelism also brings challenges in communication, both at the software and hardware level, said Markus Levy, founder and president of EEMBC. The use of MultiBench supported this research: to better understand the behavior of parallel applications and to derive representative traffic profiles for benchmarking network-on-chip designs.
The work on this white paper by our Network on Chip Working Group (supported by EEMBC), showcases co-operation and collaboration among both our industry and academic researchers, ensuring synergy advantages in the field of NoCs, said Ian Mackintosh, president and chairman of OCP- IP. We are extremely proud to host our Working Group forum where the worlds most prestigious universities and industry researchers in the field of NoC investigation come together to find common benchmarks for the industry as a whole.
For a copy of the white paper and accompanying results spreadsheet, please see http://www.ocpip.org/white_papers.php.
For more information about EEMBC MultiBench, please see http://www.eembc.org/benchmark/multi_sl.php.
For all the latest information on OCP-IP please see our latest newsletter at: www.ocpip.org/newsletters.php.
Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.OCPIP.org.