Ed Sperling, Semiconductor Engineering
June 26th, 2014
Too many choices and uncertainty turn ROI for new chip architectures into riskier gambles—and force a rethinking of what’s next.
Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and improved architectures?
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