eASIC Announces Nextreme-3 Platform Support for PCIe Gen 3.1 - SRIS
Nextreme-3 enables scalable, high bandwidth, cabled connectivity with SATA-Express using PCIe Gen 3.1
SANTA CLARA, Calif. – August 11, 2015 – eASIC® Corporation (@easic), a fabless semiconductor company that delivers a custom integrated circuit (IC) platform (eASIC Platform) today announced immediate availability of silicon-proven transceivers optimized for the PCIe 3.1 electrical specification.
The eASIC Nextreme-3 family incorporates transceivers that feature advanced receiver clock-data recovery (CDR) circuits, enabling them to operate with separate reference clocks between link ends with independent spread-spectrum modulation, in keeping with the SRIS (separate refClks independent spread) usage model. Coupled with advanced equalization capabilities and low power consumption, the transceivers are ideal for use in a wide variety of high performance storage and networking systems.
eASIC support for SRIS allows data communication over a cable without requiring a separate cable for forwarding the reference clock, which significantly reduces electromagnetic interference (EMI) issues while allowing use of lighter, lower cost cables. It also provides scalable, high bandwidth connectivity and compatibility with future SATA/SAS [serial advanced technology attachment/serial attached SCSI (small computer system interface)] standards.
“Our eASIC Nextreme-3 platform now offers designers the freedom to create server-independent, scale-out storage solutions,” said Brent Przybus, senior director of marketing at eASIC. “The small footprint of our devices, together with versatile configuration options, gives OEMs a compact, low cost and low power solution.”
About eASIC
eASIC is a semiconductor company offering a differentiated solution that enables us to rapidly and cost-effectively deliver custom ICs, creating value for our customers’ hardware and software systems. Our eASIC solution consists of our eASIC platform which incorporates a versatile, pre-defined and reusable base array and customizable single-mask layer, our ASICs, delivered using either our easicopy or standard ASIC methodologies, and our proprietary design tools.
We believe this innovative technology allows eASIC to offer the optimal combination of fast time-to-market, high performance, low power consumption, low development cost and low unit cost for our customers. eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Crescendo Ventures, Seagate Technology, Kleiner Perkins Caufield and Byers (KPCB) and Evergreen Partners.
|
Related News
- ASMedia Technologies Achieves Industry's First SuperSpeed USB 10 Gbps (USB 3.1 Gen 2) Certified Silicon (PCIe to USB 3.1 Gen 2)
- MIPI M-PHY 4.1 IP, UFS 3.1 Controller IP & Unipro 1.8 Controller IP Cores are available for instant licensing to support your total UFS applications
- eTopus Announces PCIe IP Gen 1-6 and 800G Support For 7/6nm With Support For SoC & Chiplet Clients
- Northwest Logic's Expresso 4.0 Controller Core and Fidus Systems' Zynq UltraScale+ Platform demonstrates PCIe 4.0 Support
- Solid State System Co., Ltd. selects Andes AndesCore N9 for Its SSS6131 USB 3.1 Gen 1 Flash Controller Highly Demand for Storage Application
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |