eMemory Announces the First Verified NeoFuse OTP IP in 16nm FinFET Plus Process
Hsinchu, Taiwan (Sept. 15, 2015) – eMemory announces its new technology breakthrough–the availability of its One-Time Programmable (OTP) NeoFuse technology in mainstream 16nm FinFET Plus process, as well as the development and verification of high-capacity (256k bit) and low-voltage (<0.8V) silicon IPs. It is the world’s first OTP technology verified in 16nm FinFET Plus process. eMemory also proves that its NeoFuse technology can follow Moore’s Law, scaling down beyond 16nm.
eMemory’s NeoFuse technology features “Short Time One-Pulse” data programming, unlike conventional anti-fuse OTP technologies require multiple-pulses programming that disturbs the accuracy of programmed data and requires longer programming and verification time, therefore result in higher coding cost and reliability issues.
eMemory’s 16nm NeoFuse IP works at single ultra-low voltage. Operating at ultra-low voltage enables the handshaking of signals before system is activated, which enhances data protection and security for mobile payment and IoT-related applications. NeoFuse IP is able to run on a single low voltage instead of dual voltages, thereby significantly alleviates design complexity of customer’s SoC products.
eMemory has completed high-capacity and low-voltage NeoFuse OTP IP verification in 16nm FinFET Plus process. It will be officially unveiled at the TSMC 2015 Open Innovation Platform (OIP) Ecosystem Forum in Santa Clara, California, on September 17, 2015. This exciting innovation, which has led eMemory to the forefront of the industry, also marks an important milestone as the world leader in logic non-volatile memory technology.
About eMemory:
eMemory (Stock Code: 3529) is a global leader in logic process embedded non-volatile memory (eNVM) silicon IP. Since established in 2000, eMemory has been devoted to research and development of innovative technologies, offering the industry’s most comprehensive platforms of patented eNVM IP solutions include NeoBit (OTP Silicon IP), NeoFuse (Anti-Fuse OTP Silicon IP), NeoMTP (1,000+ Times Programmable Silicon IP), NeoFlash (10,000+ Times Programmable Silicon IP), and NeoEE (100,000+ Times Programmable Silicon IP) to semiconductor foundries, integrated devices manufacturers (IDMs), and fabless design houses worldwide. eMemory’s eNVM silicon IPs support a wide range of applications include trimming, function selection, code storage, parameter setting, encryption, and identification setting. The company has the world’s largest NVM engineering team and prides itself on providing partners a full-service solution that sees the integration of eMemory eNVM IP from initial design stages through fabrication. For more information about eMemory, please visit www.ememory.com.tw.
|
eMemory Technology Hot IP
Related News
- eMemory Announces Industry's First 16nm FinFET Compact (FFC) Process Verified OTP Silicon IP
- eMemory NeoFuse Technology Is Verified in 16nm FinFET Process
- eMemory's NeoFuse IP Verified in TSMC 10nm FinFET Process
- eMemory Collaborates with Renesas on the Development of its Pure 5V OTP IP Using 130nm BCD Plus Process for Automotive Applications
- eMemory's NeoFuse Qualified on Winbond 25nm DRAM Process
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |