Avery Design Systems Announces SimRegress and SimCompare
TEWKSBURY, MA. -- June 28, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimRegress and SimCompare for improved simulation verification productivity.
SimRegress provides the ability to capture and replay the simulation testbench stimulus without having to run the full testbench thus supporting improved methods for 3rd party IP debug using tests directly from the customer SoC verification environment. Converters from the Avery database to Verdi FSDB and SimVision are supported to generate and inspect the waveforms.
SimCompare provides a smart diff feature between RTL and gate-level simulation. SimCompare correlates RTL and gate-level signal names and transaction synchronization between the two simulations being compared. The SimDiff application is integrated with Verdi and SimVision to directly scope these respective waveforms and source code debug tools and windows for more detailed inspection.
|
Avery Design Systems Hot Verification IP
Related News
- Avery Design Debuts CXL Validation Suite
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Avery Design Systems Announces SimXACT-SA™ for Improved Sequential X-Verification
- Siemens expands industry-leading integrated circuit verification portfolio with acquisition of Avery Design Systems
- Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |