SmartDV to Exhibit at OpenPower Summit August 19-20
Will Feature First Commercially Available OpenCAPI Verification IP
SAN JOSE, CALIF –– August 13, 2019 –– SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation emulation, field programmable gate array (FPGA), formal models and post-silicon validation platforms, Design IP and rapid customized VIP and Design IP development will feature the first commercially available OpenCAPI Verification IP compatible with the OpenCAPI 3.0 and 3.1 standard at the OpenPower Summit.
WHEN: Monday and Tuesday, August 19 and 20. Attendees can schedule demonstrations through: demo@smart-dv.com
WHERE: Manchester Grand Hyatt, San Diego, Calif.
SmartDV’s OpenCAPI Verification IP verifies OpenCAPI interfaces and includes an extensive test suite that performs random or directed protocol tests to create a range of scenarios to effectively verify the design under test. It supports all major verification languages and methodologies, including open verification methodology (OVM), universal verification methodology (UVM) and SystemC.
About SmartDV
SmartDV™ Technologies is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Verification and Design IP are compatible with all verification languages, platforms and methodologies supporting all simulation, emulation and formal verification tools used in a coverage-driven chip design verification flow. The result is Proven and Trusted Verification and Design IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit SmartDV to learn more.
|
SmartDV Technologies Hot IP
SmartDV Technologies Hot Verification IP
Related News
- Andes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023
- OPENEDGES To Exhibit its 4-/8-bit mixed-quantization NPU IP at Embedded Vision Summit 2022
- SmartDV to Exhibit at Virtual Samsung SAFE Forum 2020 with Portfolio of Design and Verification IP
- Chips&Media to Exhibit at the 2020 Embedded Vision Summit
- SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit
Breaking News
- CAN FD Controller & LIN 2.1 Controller IP Cores, Available for Immediate Licensing with Proven Automotive Compatibility
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- TSMC Celebrates 30th North America Technology Symposium with Innovations Powering AI with Silicon Leadership
- TSMC plans 1.6nm process for 2026
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
E-mail This Article | Printer-Friendly Page |