| Good grief! Over the last few weeks I've been exposed to more information on high-speed serial interconnect technologies -- especially PCI Express -- than my poor old brain can handle (I still remember when a board with a 1MHz system clock was pushing the bounds of "design as we know it"). |
The point is that, for many folks, the bottleneck in digital IC/SoC designs is moving away from core application logic to high-speed interfaces and interconnect. Just how does one go about designing PCI Express interfaces, and how do you verify them so as to ensure that they will function correctly, at the required speed, the first time?
Different bits and pieces
But before we plunge into the fray, let's refresh our minds as to the various bits and pieces that are involved. Let's assume that we are designing a digital chip (which could be an ASIC, structured ASIC, or FPGA) and that we've decided to use PCI Express as our high-speed serial interconnect technology. For the purposes of this discussion, we can visualize the chip as containing three main "chunks" (Figure 1).
First of all we have the "secret sauce" application logic that we (the design engineers) are creating to make us (or the companies we work for) rich beyond our wildest dreams. This logic talks to the digital (Port Logic) portion of the PCI interface, which in turn chitchats with the analog physical (PHY) layer (this latter portion includes the SerDes -- serialization/de-serialization -- functions and defines the electrical interface to the outside world).
Figure 1 -- High-level view of a chip boasting a PCI Express interface
Implementing and verifying the Port Logic core
Now let's consider the various possible scenarios when it comes to implementing the PCI Express port. In the case of the Port Logic itself, we may opt to design this little rapscallion ourselves. This is certainly the strategy adopted by the first wave of "big boys" who are currently racing to get silicon out of the door. But PCI Express is a phenomenally complex beast, so most of the other system design houses will typically look around to acquire this core in the form of silicon IP.
But where would one turn to for this sort of thing? Well, one company that is well worth talking to is Cascade Semiconductor with their CascadeXpress offering. CascadeXpress comprises a suite of cores that are modular, configurable, and highly scalable. In turn, this means that these cores can be used to address PCI Express Endpoint (EP), Root Complex (RC), and Switch (SW) implementations.
Cascade boasts that their CascadeXpress cores feature ultra-low power, low latency, small gate counts, and extremely high accessible bandwidth. Also, that their modular and configurable nature means that these cores are applicable to ASIC, structured ASIC, and FPGA implementation technologies.
CascadeXpress is used to power Agilent Technologies' PCI Express compliance testing solutions, where these solutions are used for compliance testing at PCI-SIG Compliance Workshops. This obviously adds some weight to Cascade's claim that CascadeXpress is "the de facto standard for PCI Express Design IP."
Of course once you have the PCI Express logic embedded in your IC/SoC design, you need some way to verify that it's going to work as planned. The key point here is that the very last thing you want to do is to create your own verification suite for something like PCI Express. Instead, you need to turn to someone who specialized in Verification IP, such as Denali Software, whose solutions were discussed in my April 2004 column "VIP verifies PCI Express."
Implementing and verifying the PHY layer
In the case of the PHY layer, this is the biggest piece of "black magic" in the system (it makes my eyes water just to think about it). Designing this type of thing is so horrendously painful that there are very few -- maybe only 20 -- companies in the world who would even contemplate taking on this challenge. This means that, unless you actually work for one of these companies, you are almost certain to purchase the PHY Design IP core from a third-party in the form of a hard macro.
The important point to note is that, even though your PHY Design IP vendor is giving you a hard macro (along with relevant portions of the SPICE netlist), you can vary the placement, decide whether to use dedicated or shared power, determine how the power gets onto and is distributed throughout the chip, and so forth.
All of this means that you need some way of verifying the electrical/PHY portion of the interface. And more than this, you can't afford to leave any slack on the table, so sufficiently accurate analysis of your PHY implementation can be used to modify the constraints for the digital (Port Logic) portion of the interface and to feed these new constraints back to the digital designers.
Sad to relate, however, verification IP for the PHY layer of PCI Express is an area that is not widely addressed at this time. This is where a company called Knowlent leaps boldly onto the center stage and proclaims a leadership role.
Until recently, Knowlent's customers were the giants in the PHY arena -- the ones who are designing their own PHY layers for internal use or to sell as Design IP to other system houses. In the case of extremely complex interconnect technologies like PCI Express, however, the verification of the electrical/PHY portion of the design is obliged to move into the mainstream.
Knowlent's verification IP in this arena includes piecewise linear waveforms in Spice; pre-configured measurements (about 100 different measurements for any given configuration); ways to create appropriate stimulus (including variations); ways to control simulations (change corners and templates and run tens, hundreds, thousands, or tens of thousands of simulations); and ways to post-process and analyze the results from these simulations. (Knowlent also offers consulting services, which can be very valuable for small design houses.)
I tell you, interconnects were so much simpler in my youth. In those Halcyon days of yore, we would simply run a multi-bit bus around the board and hook multiple devices onto it with reckless abandon -- and most of the time we were happy campers. The complexity of the interconnect technologies coming online today makes my hair stand on end, so I'm grateful that someone out there -- in the form of companies like Cascade, Denali, and Knowlent -- actually has a clue as to how to make all of this happen. Thus, I have no hesitation whatsoever in bestowing an official "Cool Beans" on each and every one of the little scamps. Until next time, have a good one!
Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.