The 12-Bit 20MS/s Dual Current Steering DAC employs a current steering architecture with differential current outputs. It uses 7 linear bits and 5 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit dual DAC features an excellent static performance that includes ±0.8LSB DNL and ±1.0LSB INL.
Dynamic performance highlights considering a signal frequency with 600KHz and 20MS/s conversion rate include an SNR of 74dB and an SFDR of 80dBc over 1.2MHz bandwidth.
The 12-Bit 20MS/s Dual Current Steering DAC is designed in a 180nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- 12-Bit 20MS/s Dual Current Steering DAC
- 180nm TSMC G Process, 6 Metals
- No Analog Options
- 3.3V and 1.8V Supplies
- Sampling Rate up to 20MS/s
- 2.0Vpp Differential Output Range
- DNL< 1.0LSB
- INL< 1.0LSB
- High Performance at 20MS/s over 1.2MHz BW
- SNR = 74dB, SFDR = 80dBc, FOUT = 600KHz
- Stand-By and Power-Down Modes
- Compact Die Area
Block Diagram of the 12-Bit 20MS/s Dual Current Steering DAC - TSMC 180nm