1Gbps-11.35Gbps Multi-Rate SerDes

Features

• • Data Rate: 1Gbs – 11.35Gbs
• • Serial Interface complies with XFI/SFP/SFP+ MSA Specifications
• • Transmit clock generation PLL with jitter attenuation capability to comply with Telecom (SONET/SDH, OTN ITU-T G.709) and DataCom (Gigabit and 10Gigabit Ethernet) standards
• • Clock and Data Recovery (CDR) at the receive direction
• • Equalization on the receive side
• • Low input sensitivity
• • Receive Threshold adjustment for LOS support
• • Receive LOS (Loss Of Signal) Detect indication
• • Lock Detect Indication in Rx CDR and Tx PLL
• • Line and Terminal loopback on the serial side and Line loopback on the parallel bus
• • On-chip termination resistors
• • Four SERDES elements are packed in a Quad SERDES core
• • Low power
• • Small area
• • TSMC 65nm (GP) process, 2.5V IO MOS

Benefits

• • The ACEIC9200MSerDes employs high performance equalization schemes capable of working with high-loss backplanes in wide variety of communication protocols.
• • ACEIC9200MSerDes utilizes small area and dissipates low power.

Deliverables

• GDSII
• Netlist
• .LIB
• VERILOG model
• Integration guidelines