The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target peripherals. Its optional scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface.
- AXI4 and AXI4-Stream compliant
- Optional Scatter/Gather (SG) DMA support
- When Scatter/gather mode is not selected the IP operates in Simple DMA mode.
- Primary AXI4 Memory Map and AXI4-Stream data width support of 32, 64, 128, 256, 512, and 1024 bits
- Optional Data Re-Alignment Engine
- Optional AXI Control and Status Streams
- For use with Xilinx CORE Generator™ and Xilinx Embedded Development Kit (EDK)