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Bluetooth Baseband Controller V2.1+EDR

The Bluetooth Baseband Controller V2.1+EDR is a full featured fully compliant implementation of the V2.1+EDR specifications. The Bluetooth Baseband Controller IP is available as ready-to-integrate Synthesizable Verilog RTL code, together with C Source code for the lower stack, test vectors and synthesis scripts.

The Bluetooth Baseband V2.1+EDR comes with a rich set of complimenting packages such as BQB qualified upper stack and profiles, integrated reference designs and PC-based Test application with comprehensive tets suites.

Features

Full Implementation of V2.1+EDR
Low Power & Gate Count
Feature Rich:

AFH, Faster Connectivity and ESCO
ESCO - all packet types up to 6 connections
Support for 79 and 23 hop sequences
Support for HW and SW codecs
SCO/ESCO Transparent mode support

Flexible and efficient Architecture:

Configurable for no. of links and RAM
Configurable for different radios
Low gate count
Very Compact ROM and RAM
Under 5 MIPS of CPU load (ARM7)
Full on-the air data rate of 723.1kbps

Easy to Integrate:

Available for AMBA bus
Interface to other CPUs avaialble on request
Choice of Radios (SiliconWave, Ericsson, Fujitsu)
Most portable LMP and LC firmware: RTOSes - AMX, µCOS-II, Windows CE 4.2 & .NET

Benefits

Highly customizable Silicon IP allows product differentiation
Most portable lower stack firmware allows choice of OS best suited for the product
Ease of integration with SOCs gives time to market advantage to licensees
Being one-stop-shop for complementary blocks - upper stack, profiles, test and pre-qualification applications, Echo Cancellation and Noise reduction algorithms and audio codecs (CVSD, SBC) - gives licensees complete control over integration and product realization
Choice of licensing options that makes the best business sense.

Deliverables

Synthesizable Verilog RTL code
Test bench with simulation models for CPU, Codec and Radios
Comprehensive test suite including prodcution test vectors
Synthesis scripts
C Source code for lower stack (HCI, LMP and LC)
HW Implementation Document
Verification Document
Integration Manual
FPGA-based validation platform with Firmware and demo application
Schematics and Board User Manual

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