Low Power 32-bit DSP Architecture Framework for Advanced Audio and Voice Applications

CEVA-TeakLite-4 is a low-power, native 32-bit, variable 10-stage pipeline, fixed-point DSP architecture framework. The CEVA-TeakLite-4 is a fully synthesizable, process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency.

The CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421 DSP cores are based on, and compliant to, the high-performance, low-power CEVA-TeakLite-4 DSP architecture.

With a primary target of standalone DSP chips used to implement audio CODECs, audio D-Class amplifiers, and noise-reduction chips, the ultra-low-power CEVA-TL410 DSP core offers the smallest die size with its single 32x32-bit MAC, dual 16x16-bit MACs, and direct memory interface. If higher performance is required, the CEVA-TL411 core provides dual 32x32-bit MACs and quad 16x16-bit MACs.

Alternatively, for CPU-centric SoCs, such as the application processors and main SoCs used in smartphones, digital televisions (DTVs), set-top boxes (STBs), and game consoles, the CEVA-TL420 augments the features of the CEVA-TL410 with data and instruction cache controllers and a master/slave AXI system interface (the CEVA-TL421 augments the CEVA-TL411 with the same high-end capabilities). All CEVA-TeakLite-4 architecture-compliant cores are fully compatible with each other and with previous generation CEVA-TeakLite family cores.