The Synopsys DesignWare® USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low power mobile and consumer applications game machines, feature rich smart phones, digital cameras and portable audio/video players. The DesignWare USB 2.0 nanoPHY IP delivers approximately half the power and die area, compared to other solutions, for longer battery life and lower the DesignWare USB 2.0 nanoPHY implements architectural features that make it less sensitive to variations in foundry process, device models, package and board parasitics. Designed for advanced manufacturing processes, the USB 2.0 nanoPHY is targeted to leading 40nm, 45nm, 65nm, 90nm, and 130nm low power (LP) CMOS digital logic processes.
Features
- Low pin count
- USB 2.0 Transceiver Macrocell Interface (UTMI+ Level 3) specification
- Supports all OTG features, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
- On-chip PLL reduces clock noise and eliminates external clock generator requirement
- Built-in Vbus pulsing and discharge SRP circuitry
- Please contact Synopsys for specific area and power numbers
Benefits
- Ported to over 50 different processes and configurations ranging from 180-nm to 28-nm
- USB nanoPHY and USB picoPHY offers a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
- USB 2.0 PHYs support Device, Host and OTG configurations
- Low power, small area, high yield
Deliverables
- GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
- Simulation model for digital blocks, Behavioral models for analog blocks
- Synopsys’ PrimeTime STA results, Gate-level netlist and SDF timing file
- DesignWare USB 2.0 nanoPHY Databook
- Digital test vectors (.wgl); scan test environment with Automatic Test Pattern Generation (ATPG) vectors
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