Wireless USB device controller is designed to be used in a system to provide Wireless USB connectivity between the device it is being used and the Wireless USB host. This IP is designed based on the Wireless USB specification 1.0 and is compliant with the ECMA 369/368 UWB Phy interface standard. Hence the Wireless USB device controller may be used very easily in any SOC environment with out any issues. On the processor side is able to interface with industry standard AMBA AHB and AXI bus and also supports Altera defined Avlon bus. This makes this IP easily integrated in any SOC that has one of this industry standard bus architecture. This Wireless USB device controller is developed and verified using Verlilog HDL. Fully synthesizable RTL with test bench is the part of deliverables.
- Fully compliant with wireless USB 1.0 specification.
- Fully compliant with ECMA 369/368 UWB Phy-MAC interface specification.
- Support all transfer types - Control, Bulk, Isochronous and Interrupt transfers.
- Maximum of 7 endpoints. Endpoint 0 is for control transfer and rest are for data transfers.
- Endpoints are fixed for a type of data transfer.
- Support industry standard 32 bit bus interface - AMBA AHB/AXI or AVLON etc.
- Supports power saving features like sleep mode.
- Supports an on chip Endpoint buffer and also an external buffer. which helps in improving stream delay for Isochronous data transfer.
- Supports only out of band security key exchange mechanism.
Block Diagram of the Wireless USB Device Controller