JEDEC UFS Device Verification Solution - Full test bench with BFM and directed and constrained random test suites
The JEDEC UFS 2.0 Device Verification IP (VIP) de-risks your JEDEC UFS-2.0 Device development effort by providing a high degree of confidence over all the design features before shipping silicon. JEDEC UFS-2.0 is a verification challenge as it has to support several UFS SCSI commands, task management commands and interaction with the underlying service delivery mechanism that consists of MIPI UniPro 1.6 and MIPI M-PHY 3.0. Our JEDEC UFS-2.0 Verification IP provides the relevant BFMs and a full feature test-bench with ready-made compliance and random test-suits, coverage and assertion suits.
Specification: JEDEC UFS 2.0
UVM test-bench with pre-written compliance and constrained random test suite
BFM implementation: Native SystemVerilog
BFM methodology Support: UVM, OVM, VMM
Simulator support: Synopsys VCS, Mentor Graphics Questa
Configurability: Supports both the UFS Host and Device Verification