The MIPI M-PHY Verification IP is fully compliant with Standard MIPI M-PHY Version 2.0 specifications from MIPI Alliance.
The MIPI M-PHY Verification IP provides an effective & efficient way to verify the components interfacing with MIPI M-PHY interface of an ASIC/FPGA or SoC.
This Verification IP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.
- Compliant to MIPI M-PHY Version 2.0.
- M-PHY Supports two Sub-links.
- Supports high speed and low speed mode for all
- HS-MODE Supports HS-BURST with all HS-Gears HSG1,
- HS-G2, HS-G3.
- HS-MODE Supports both data rate Series A and
- LS-MODE Supports both MODULE-I and MODULE-II
- LS-MODE MODULE-I supports PWM-signaling with all
- PWM-Gears PWM-G0, PWM-G1 up to PWM-G7
- LS-MODE MODULE-II supports NRZ-Signaling.
- Configurable number of lanes for each Sub-link.
- Supports protocol interface i.e. RMMI Interface.
- Supports 8b 10b encoding in Tx and decoding in Rx.
- Supports bypassing of 8b 10b encoding and decoding.
- Supports callbacks in transmitter and receiver.
- Supports wide variety of Error Injections.
- Supports protocol monitor real time exhaustive checks.
- Supports assertion for protocol checks.
- Supports coverage of different state transition.
- Available in native System Verilog (UVM/OVM/VMM) and Verilog
- Complete Verification of MIPI CSI-2 designs
- Improvement in Verification productivity
- Lower rate of re-spin
- MIPI M-PHY Verification IP
- Test Suite in source code
- User Guide and Release Notes
Block Diagram of the MIPI M-PHY Verification IP