USB 2.0 Vera RVM VIP speeds up the verification process providing a compelling cost and time to market.
This VIP is developed using the Synopsys’ Vera Reuse Verification Methodology that is used in dynamic simulation of USB 2.0 based design.
USB 2.0 Vera RVM VIP can work in a standalone mode i.e. can be plugged with any Function Controller with standard pinouts without disturbing the structure.
- Synopsys RVM compliant
- The VIP can work with 8 bit or 16 bit standard USB devices
- Absence of inter-module dependencies makes it highly reusable
- Following USB 2.0 Modes are being supported:
- Full-Speed / High-Speed - 8-bit
- Full-Speed / High-Speed - 16-bit
- Programmable and Randomized Transfer Types, namely, INTERRUPT, ISOCHRONOUS, BULK and CONTROL Transfer Types
- Auto Programming – cum selection of Clocks for different Modes
- Hierarchical Seed Randomization. Common Seed to all Randomized tasks.
- Fully Constrained Driven Randomization of Packets achieved by Randomization of various fields of the Packet
- Presence of a DUT Health check-up mechanism during initialization
- Provides a choice for inhibiting SUSPEND and / or RESET operation through use of simple macros
- Supports up to 16 Endpoints as per the USB 2.0 Standard. Endpoints can be either IN, OUT or NOT_IMPLEMENTED through user-defined header declarations, with Endpoint 0 as INOUT
- The product is bundled with a very fancy, intelligent and versatile Scoreboard
- The VIP provides a fast, accurate way to simplify and speed-up the device verification task. In a complex design process, verification may take up to 70% of the development time. USB 2.0 Vera RVM VIP speeds up the verification process providing a compelling cost and time to market.
- Writing a reusable code makes it easy for the Verification Engineer to apply the same tasks in various modules from project to project.
- Complete test environment
- Vera Source
- Reference Manual