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New Silicon IP
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Scalable UHD JPEG 2000 Encoder - 8 up to 16 bits per Component Lossy or Numerically Lossless Image / Video Compression
- ISO/IEC 15444-1 Compliant and Standalone Operation
- Advanced JPEG 2000 Implementation
- Easy Implementation and Verification
- Trouble-Free Technology Map and Implementation
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8/16-Bit Microcontroller Based on the W65C816
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8-Bit Microcontroller Based on the W65C02
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8-Bit Microcontroller Based on the W65C02
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Video Codec IP using RAW input (CFA)
- Low complexity for ASIC & FPGA
- No external DDR (optional)
- Extreme low latency
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Deterministic Random Bit Generator (DRBG)
- NIST 800-90A/B/C compliant
- Health test
- AES-CTR based (CTR_DRBG)
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Blockchain Hardware Accelerator
- Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
- Ideal for FPGA/ASIC integration
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IEEE 802.11i MAC
- SoC architecture
- Scalable solution
- On demand customization available
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Crypto Coprocessor
- Scalable architecture and crypto engines for optimal performance/resource usage
- Configurable for perfect application fit
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ARIA Crypto Engine
- Supports a wide selection of programmable ciphering modes
- Supports encryption & decryption
- Supports 128-bit, 192-bit & 256-bit key sizes
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PGA IP core T-COR-32 is designed to solve the problems of targeting and targeting. The IP core is used in unmanned aerial vehicles, combat modules, fire control systems, fire control systems and target designation systems.
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Video Tracking FPGA IP core for Xilinx and Altera
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