New Silicon IP
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14-stereo AAC-LC Audio Encoder
- All encoders use the Fraunhofer IIS software
- Configurable output latency useful to synchronize with other sources (up to 8 frames)
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Pulse Per Second (PPS) Clock to PPS core
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DisplayPort 1.4 IP-core
- Compact RTL footprint
- Easy-to-use
- Simple API
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IP Camera Front End
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Configurable Ascon IP for FPGA and ASIC
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Configurable CAN Bus Controller with Flexible Data-Rate
- Designed in accordance with ISO 11898‐1:2015 specification
- Supports CAN and CAN FD frames
- Supports up to 64 bytes of data frame
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Time aligned Frequency Generator core
- Configurable frequency signal generation (0-10MHz) in 1Hz steps
- Configurable polarity
- Output delay compensation
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Generic Waveform Generator
- Scalable approach
- Huge set of supported protocols
- Variable set of driver ans stimuli units possible
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Enhanced Multiprotocol Serial Communication Controller
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
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DCD's Universal Timers System
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Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
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SMBUS & PMBUS Master/Slave controller
- Master operation: Master transmitter, Master receiver
- Slave operation: Slave transmitter, Slave receiver
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