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IEEE 802.11ah MAC/PHY

• 1 MHz and 2 MHz channel width
• S1G_1M, S1G_SHORT PPDU
• Mandatory MAC including TXOP, RID, SST, TWT, AID,…, RAW

Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component

• Flexible and independent clocks for control-plane and reference clock
• Up to 32 outputs, each in their own clock domain

Deep captureDebug IP for Intel FPGA

• Configurable upstream link, up to 4 transceivers at 12.5 Gbps each.
• Downstream link to configure IP triggers and data group

Multi-Channel DMA Engine for Virtualized Systems

• Up to 2048 DMA channels, extensible upon request
• Up to 512 Virtual Machines, extensible upon request
• AMBA AXI4 interfaces with 256-bit data path

DPDK-aware FPGA/GPP data mover

• Line rate agnostic: Operates at any line rate, including 1/5/10/25/40/50/100/400 GbE
• Up to 150 Gbps and 120 Mpps with a contemporary PCIe Gen3x16 interface, Gen4 Ready

Video Tracking FPGA IP core for Xilinx and Altera

• Tracking up to 80 fps at core clock frequency 300 MHz and object size of 128x128 pixels.
• The IP core implements 1 tracking channel. If sever-al channels are required, several cores need to be used.

Video Tracking FPGA IP core for Xilinx and Altera

• Tracking up to 80 fps at core clock frequency 300 MHz and object size of 128x128 pixels

LEON3FT Fault-tolerant processor

• Register file SEU error-correction of up to 4 errors per 32-bit word
• Cache memory error-correction of up to 4 errors per tag or 32-bit word

1G TCP Offload Engine TOE Very-Low Latency (TOE)

USB 3.1 Gen 2 Device Controller

• Software Enumeration
• FIFO Interface

Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface

• Complies with the PCI Express Base 4.0 Specification,
• Supports Endpoint and rootport configuration
• Supports x16, x8, x4, x2, x1 at Gen4, Gen3, Gen2, Gen1 speeds

SATA 2 HOST ON CYCLONE 5 GX

• Compliant with Serial ATA II specifications
• Fixed Speed 3Gbs or 1.5Gbs