Search IP on Altera

Configurable CAN Bus Controller with Flexible Data-Rate

• Designed in accordance with ISO 11898‐1:2015 specification
• Supports CAN and CAN FD frames
• Supports up to 64 bytes of data frame

Time aligned Frequency Generator core

• Configurable frequency signal generation (0-10MHz) in 1Hz steps
• Configurable polarity
• Output delay compensation

Generic Waveform Generator

• Scalable approach
• Huge set of supported protocols
• Variable set of driver ans stimuli units possible

Enhanced Multiprotocol Serial Communication Controller

• Rapid prototyping and time-to-market reduction
• Design risk elimination
• Development costs reduction

DCD's Universal Timers System

Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s

• Rapid prototyping and time-to-market reduction
• Design risk elimination
• Development costs reduction

SMBUS & PMBUS Master/Slave controller

• Master operation: Master transmitter, Master receiver
• Slave operation: Slave transmitter, Slave receiver

Low-power high-speed reconfigurable processor to accelerate AI everywhere.

UART Core with SDLC Function

RSA-ECC High-Performance Multi Public Key Engine

• RSA, ECC and more
• > 1 GHz in 16nm

Network Security Crypto Accelerator

• Scalable architecture & crypto engines for optimal performance/resource usage
• Configurable for perfect application fit
• 100% CPU offload with low latency and high throughput

DDR Encrypter

• Protect the external memory
• On-the-fly encryption
• Optional authentication