Process Detector (For DVFS and monitoring process variation), TSMC N7
Early Interactive Short Isolation for Faster SoC Verification
By Ritu Walia, Siemens (December 4, 2024)
In modern semiconductor design, shrinking technology nodes and increasing circuit complexity make layout versus schematic (LVS) verification more challenging. One of the most common and critical errors designers find during LVS runs is shorted nets. Identifying and isolating these shorts early in the process is essential to meeting deadlines and ensuring a high-quality design. However, finding shorts in early design cycles can be a time-consuming and resource-intensive task because the design is “dirty” with numerous shorted nets.
To tackle this challenge, designers need a robust LVS solution to address shorts early in the design flow. This article explores common short isolation challenges and presents a novel solution that integrates LVS runs with a powerful debug environment for faster and more efficient verification.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Are you optimizing the benefits of cloud computing for faster reliability verification?
- Hardware-Assisted Verification: The Real Story Behind Capacity
- Design-Stage Analysis, Verification, and Optimization for Every Designer
- Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
- Out of the Verification Crisis: Improving RTL Quality
New Articles
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
Most Popular
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology