IP / SOC Products Articles
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SoC NoCs: Homegrown or Commercial Off-the-Shelf? (Apr. 29, 2024)
The developers of today’s system-on-chip (SoC) devices face a myriad of decisions. Some of the early choices start when defining the overall architecture of the device. Next comes the determination of which intellectual property (IP) functional blocks to be used and their origin.
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From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs (Apr. 22, 2024)
This paper attempts to address and reconcile two different issues: the existence of multiple numerical data formats (such as int8, bfloat16, fp8, etc., often non optimal for the application and not directly compatible with one another) and the necessity to reduce their bandwidth requirements, especially in the case of power hungry and slow DRAM.
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Embracing a More Secure Era with TLS 1.3 (Apr. 02, 2024)
TLS 1.3 offers attractive speed and security improvement benefits that are hard to ignore. The handshake phase was sped up by removing one or more roundtrips (back and forth messaging between client and server) in TLS 1.3 – with “or more” meaning that for certain cases, roundtrips can be entirely eliminated (0-RTT).
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Maximizing ESD protection for automotive Ethernet applications (Mar. 25, 2024)
For many decades, Ethernet has been used in industrial and computing networks. But nowadays it’s increasingly deployed in automotive applications as a replacement for legacy networks like controller area network (CAN).
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The role of cache in AI processor design (Mar. 22, 2024)
There are two main aspects to AI: training, which is predominantly performed in data centers, and inferencing, which may be performed anywhere from the cloud down to the humblest AI-equipped sensor.
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Time Sensitive Networking for Aerospace (Mar. 18, 2024)
This white paper highlights the integration of Time-Sensitive Networking (TSN) in the aerospace industry. It provides an overview of TSN standards and profiles and the IEEE P802.1DP standard relevant to aerospace applications. It also discusses key topics such as time synchronization, latency, resource management, and reliability in the context of TSN.
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Advanced Topics in FinFET Back-End Layout, Analog Techniques, and Design Tools (Mar. 07, 2024)
In this post, we’ll look at more advanced technology topics and key design tools that enhance layout productivity. We’ll also explore what might be next for integrated circuit (IC) mask layout design.
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Maximizing Performance & Reliability for Flash Applications with Synopsys xSPI Solution (Mar. 04, 2024)
Systems using SoCs designed in advanced processes generally rely on external Flash devices that use NOR/NAND Flash memory technology for non-volatile storage. NOR Flash memory offers many benefits for device manufacturers and consumers, such as faster reading, low power consumption, and smaller area. In contrast, NAND Flash memories are ideal for applications such as data storage, where higher memory capacity and faster write and erase operations are required.
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MIPI deployment in ultra-low-power streaming sensors (Feb. 19, 2024)
This article focuses on low-power scenarios with streaming sensors connected to a processor via MIPI. After a short overview of low-duty cycle sensor principles, we explore how a streaming image sensor leverages those principles, show how one semiconductor company uses MIPI CSI-2® and D-PHY interfaces in their imaging solution, and touch on use cases for ultra-low-power streaming sensors deploying MIPI.
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FinFET Technology and Layout (Jan. 30, 2024)
FinFETs form the foundation for many of today’s semiconductor fabrication techniques but also create significant design concerns that affect your layout. Understanding the changes and design strategies that finFET requires is crucial to building an effective layout. In this post, we’ll talk about how these changes influence integrated circuit layout.
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SoC design: When a network-on-chip meets cache coherency (Jan. 24, 2024)
Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.
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Three Major Inflection Points for Sourcing Bluetooth Intellectual Property (Jan. 22, 2024)
Synopsys is now shipping support for Bluetooth® 5.4, the latest specification from the Bluetooth SIG (Special Interest Group). The enhancements in Bluetooth 5.4 will open additional markets and use cases. This is one of the many inflection points in the Bluetooth Low Energy market that will be discussed in this paper.
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BLE Set to Dominate Indoor Positioning Systems (Jan. 11, 2024)
Indoor positioning systems – helping me figure out where I am in the mall, where is the specific item I want to buy, where is the latest shipment of iPhones in this warehouse – this is a need still not well met through existing solutions.
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Optimizing Communication and Data Sharing in Multi-Core SoC Designs (Jan. 08, 2024)
As semiconductor manufacturing technology advances, systems-on-chip (SoCs) have increased our capacity to contain more transistors in a smaller area, enabling greater computational power and functionality. The way of connecting components in an SoC needed to evolve to support the growing data communication demands.
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5 Steps to Confront the Talent Shortage With IP-Centric Design (Jan. 05, 2024)
One way to help alleviate the effects of the talent shortage is changing how semiconductors are designed so that organizations can achieve more with their existing workforce. This requires moving away from project-centric design and transitioning to an IP-centric design methodology. But why make this switch?
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How to Elevate RRAM and MRAM Design Experience to the Next Level (Dec. 19, 2023)
This article will explore the potential advantages of RRAM and MRAM in various applications and elucidate why such new technologies are imperative to address future memory demands, as well as some challenges designers may encounter in the implementation.
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The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes (Dec. 11, 2023)
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
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LPDDR flash: A memory optimized for automotive systems (Dec. 05, 2023)
Next-generation automotive systems are advancing beyond the limits of currently available technologies. The addition of advanced driver assistance systems (ADAS) and other advanced features requires greater processing power and increased connectivity throughout the vehicle.
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Menta eFPGA IP for Edge AI (Nov. 16, 2023)
The paper is divided into two main sections: the first one deals with AI algorithms, with a particular focus on Artificial Neural Networks (ANNs), which are widely acknowledged as the most commonly employed techniques in the field. The second part of the paper shifts its focus to their hardware implementation, where three distinct hardware categories are evaluated: general-purpose processors, specialized AI chips, and programmable systems.
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Extending network-on-chip (NoC) technology to chiplets (Nov. 15, 2023)
The majority of today’s ICs employ some form of NoC, but how will the NoC-based chiplets communicate with each other?
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Inside HDR10: A technical exploration of High Dynamic Range (Nov. 06, 2023)
High Dynamic Range (HDR) technology has taken the world of visual entertainment, especially streaming media solutions, by storm. It's the secret sauce that makes images and videos look incredibly lifelike and captivating. From the vibrant colors in your favourite movies to the dazzling graphics in video games, HDR has revolutionized how we perceive visuals on screens.
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Streamlining SoC Integration With the Power of Automation (Oct. 23, 2023)
The rapid acceleration of semiconductor technologies is creating system-on-chip (SoC) devices that are increasingly complex. These chips contain billions of transistors and hundreds of functional intellectual property (IP) blocks.
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The Challenge of Automotive Hardware Security Deployment (Oct. 02, 2023)
A complete reinvention of the automotive industry is currently underway. Autonomous driving, connected vehicles, and the electrification of the powertrain all represent a once-in-a-generation shift in the manufacturing process.
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Off-the-Shelf Chiplets Open New Market Opportunities (Sep. 21, 2023)
With the reintroduction of semiconductor integration into system development, standards-based chiplets promise more efficient, cost-effective designs.
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Accelerating RISC-V development with network-on-chip IP (Sep. 21, 2023)
In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.
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Efficient FIR filtering with Bit Layer Multiply Accumulator (Sep. 18, 2023)
Bit Layer Multiplier Accumulator (BLMAC) is an efficient method to perform dot products without multiplications that exploits the bit level sparsity of the weights. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255.
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The benefit of non-volatile memory (NVM) for edge AI (Sep. 18, 2023)
In low-power IoT and edge AI applications, AI models can be small enough to fit into the internal NVM of an SoC. The on-chip NVM could be used for both code storage and to hold the AI weights and CPU firmware.
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What This Year May Well Bring for the eFPGA (Sep. 18, 2023)
We think 2023 will be another exciting year in eFPGA, and these are our top 5 predictions on what to expect:.
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I2C Interface Timing Specifications and Constraints (Sep. 11, 2023)
This paper covers the timing specification of I2C (Inter-Integrated Circuit) bus protocol. We have described all the timing specifications and how they are achieved by constraining our design. This paper focuses on the timing constraints for fast mode plus (The data transfer rate is 1 Mbit/s).
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Handling the Challenges of Building HPC Systems We Need (Sep. 07, 2023)
What is the secret of humanity’s success? What has given us the ability to build wonders, such as Stonehenge in England, the Pyramids of Egypt and the Great Wall of China? Humans are small, weak and slow compared with many other animals.