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Synopsys Collaborates with Google Cloud to Broadly Scale Cloud-based Functional Verification (Monday Dec. 09, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with Google Cloud to provide a full end-to-end solution to perform functional verification workloads in the cloud.
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Synopsys VC LP for Low Power Signoff Verification Delivers Up to 5X Runtime Gain at Samsung (Thursday Nov. 07, 2019)
Synopsys today announced that Samsung has adopted the Synopsys VC LP™ solution, part of the Verification Continuum™ Platform, for low-power signoff and static verification to minimize costly design iterations for large-scale, complex system-on-chip (SoC) designs.
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Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis (Wednesday Nov. 06, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Tempus™ Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity analysis and power integrity analysis tool, which enables engineers to create reliable designs at 7nm and below.
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Synopsys and AMD Execute Multi-Year ZeBu Emulation Agreement (Wednesday Oct. 30, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced a multi-year agreement with AMD to utilize its ZeBu® Server 4 emulation system, accelerating verification of the growing number of AMD high-performance processor, graphics, and gaming projects.
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Synopsys Ships More Than 3,000 HAPS-80 Prototyping Systems (Tuesday Oct. 29, 2019)
HAPS-80 is deployed at more than 100 companies worldwide, including nine of the top 10 semiconductor companies, to accelerate software development and system validation across a wide range of consumer, wired and wireless communications, industrial, AI, and computing/storage applications.
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Optima Design Automation Launches with Focus on Next-Generation Semiconductor Functional Safety Tools (Tuesday Oct. 29, 2019)
Revolutionary, High-Performance Optima Safety Platform Propels Range of High-Coverage Safety Solutions for Automotive ISO 26262 Fault Analysis.
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Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety (Monday Oct. 28, 2019)
Accellera announced today the formation of a Proposed Working Group (PWG) to focus on a standard to enable tool interoperability between Failure Modes, Effects, and Diagnostic Analysis (FMEDA) for functional safety and the design and verification flow of electronic circuits and systems.
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Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology (Friday Oct. 18, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the complete, integrated Cadence® 3D-IC advanced packaging integration flow has achieved certification for the Samsung Foundry MDI™ (Multi-Die-Integration) packaging flow based on the 7nm Low Power Process (7LPP) technology.
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Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation (Friday Oct. 18, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Samsung Foundry certified a new Cadence® reference flow for the creation of advanced-node automotive designs.
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Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology (Thursday Oct. 17, 2019)
Cadence today announced that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 5nm Low-Power Early (5LPE) process technology.
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Synopsys Design Platforms Enabled for Samsung Foundry 2.5D-IC Multi-Die Integration (Thursday Oct. 17, 2019)
Synopsys today announced availability of design solutions to support Samsung Foundry's 2.5D-IC Multi-Die Integration (MDI™) on its 7-nanometer (nm) LPP (Low Power Plus) with extreme ultraviolet (EUV) lithography technology, known as 7LPP.
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Samsung Foundry and Synopsys Deliver Comprehensive Automotive Solutions for Autonomous Driving and ADAS (Thursday Oct. 17, 2019)
Synopsys today shared details of its collaboration with Samsung Foundry to deliver comprehensive automotive chip design solutions to meet target automotive safety integrity levels (ASILs) for autonomous driving and advanced driver-assistance systems (ADAS).
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NXP to Adopt Synopsys' Native Automotive Design Solutions for Next-generation Safety-critical SoCs (Tuesday Oct. 15, 2019)
Synopsys today announced that NXP, the world leader in secure connectivity solutions for embedded applications, plans to deploy Synopsys' native automotive design solutions to improve quality-of-results (QoR) and time-to-results (TTR) for its next-generation, safety-critical system-on-chip (SoC) designs.
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Synopsys Introduces Native Automotive Solutions Optimized for Efficient Design of Autonomous Driving and ADAS SoCs (Tuesday Oct. 15, 2019)
Synopsys today announced its new native automotive solutions for more efficient system-on-chip (SoC) design. The accelerating evolution of vehicle technologies means that more automotive chips are required to satisfy higher automotive safety integrity levels (ASILs) for autonomous driving and advanced driver-assistance systems (ADAS).
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GLOBALFOUNDRIES Qualifies Synopsys Fusion Design Platform on 12LP FinFET Platform (Thursday Oct. 10, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that GLOBALFOUNDRIES® (GF®) has qualified Synopsys' Fusion Design Platform™ for its 12-nanometer (nm) Leading-Performance (12LP) FinFET platform.
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Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation "Hercules" CPU (Wednesday Oct. 09, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has collaborated with Samsung Foundry and Arm to deliver a complete, high-performance digital implementation and signoff full flow for the rapid implementation of the next-generation Arm® “Hercules” CPU using the Samsung Foundry 5nm Low-Power Early (5LPE) process technology.
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Synopsys Announces Industry-First Unified Functional Safety Verification Solution to Accelerate Time-to-Certification for IPs and SoCs (Monday Oct. 07, 2019)
Synopsys today announced the industry's first and most comprehensive unified functional safety verification solution to accelerate time to ISO 26262 certification
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SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator (Tuesday Oct. 01, 2019)
SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification Intellectual Property (VIP) provider to do so.
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Synopsys Introduces PrimeECO Solution for Zero-Iteration Signoff-Driven Design Closure (Monday Sep. 30, 2019)
Synopsys today announced the Synopsys PrimeECO design closure solution, the industry's first signoff-driven solution that achieves signoff closure with zero iterations.
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Multiple Mentor product lines now certified on TSMC's most advanced processes (Friday Sep. 27, 2019)
Today at the TSMC 2019 Open Innovation Platform® (OIP) Ecosystem Forum, Mentor, a Siemens business, announced a broad array of recently certified tools, compelling new functionalities and other foundry-specific enablement measures on TSMC’s most advanced processes intended to benefit mutual Mentor/TSMC customers and help to further expand TSMC’s growing ecosystem.
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Synopsys and TSMC Collaborate for Certification on 5nm Process Technologies to Address Next-generation HPC, Mobile Design Requirements (Thursday Sep. 26, 2019)
Synopsys today announced it has achieved certification for dozens of new, innovative features to the Synopsys Digital and Custom Design Platforms on TSMC's most advanced 5nm process technology, required for high-performance computing (HPC) and mobile chip designs
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Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies (Wednesday Sep. 25, 2019)
Cadence today announced that its digital and signoff full flow and custom/analog tools have achieved certification on TSMC’s N6 and N5/N5P process technologies.
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Breker Verification Systems Unveils Intelligent Regression Optimization Solution to Accelerate Simulation, Emulation Execution (Wednesday Sep. 25, 2019)
Breker Verification Systems, the leading provider of Portable Stimulus Standard (PSS)-compliant software, today announced its PSS-based Test Suite Synthesis includes a set of new efficiency features including Intelligent Coverage Targeting, Pre-Solve/Pre-Compile Test Application and RapidFire™ Test Scheduling.
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Imagination launches game-changing IMG Edge services platform for design verification and validation (Friday Sep. 06, 2019)
Imagination Technologies announces today that it is expanding its business with a tailored consultancy, hosting and deployment service for design and verification, called IMG Edge.
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CacheQ Debuts Heterogeneous Compute Development Environment (Thursday Sep. 05, 2019)
CacheQ Systems, Inc., a startup developing heterogeneous distributed acceleration solutions, today unveiled its QCC Acceleration Platform, a heterogenous compute development environment delivering faster performance and reduced development time for processor and field programmable gate array (FPGA) compute architectures.
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Synopsys Enables First-Pass Silicon Success of High Performance NSITEXE Data Flow Processor-based SoC Test Chip for Autonomous Driving (Tuesday Sep. 03, 2019)
Synopsys today announced that NSITEXE, Inc. achieved success with its first silicon for Data Flow Processor (DFP)-based SoC test chip by using Synopsys design, verification and IP solutions.
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Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process (Tuesday Aug. 06, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) and United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, today announced that the Cadence® analog/mixed-signal (AMS) IC design flow has achieved certification for UMC’s 28HPC+ process technology.
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Avery Design Systems Announces SimAccel FPGA Accelerator (Monday Aug. 05, 2019)
Avery Design Systems today announced availability of the SimAccel FPGA-based accelerator to achieve 100-1000X speed up over simulation-based verification.
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Cadence Introduces Conformal Litmus to Deliver Fastest Path to Full-Chip Constraints and CDC Signoff (Monday Jul. 22, 2019)
Cadence today unveiled the Cadence® Conformal® Litmus, the next-generation solution that provides constraints signoff and clock domain crossing (CDC) signoff, reducing overall design cycle times and enhancing the quality of silicon in complex system-on-chip (SoC) designs.
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Innovium Adopts the Cadence Innovus Implementation System for Its Highly Scalable Switch Silicon Family for Data Centers (Monday Jul. 22, 2019)
Cadence Design Systems today announced that Innovium, a leading provider of innovative data center switching silicon solutions, has adopted the Cadence® Innovus™ Implementation System for its 16nm TERALYNX 12.8Tbps ethernet switches for data centers.