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Synopsys and Ixia, a Keysight Business, Announce Collaboration to Enable Scalable Networking SoC Validation Solution (Thursday Jul. 18, 2019)
Synopsys, Inc. (Nasdaq: SNPS) and Ixia, a Keysight Technologies, Inc. (NYSE: KEYS) business, today announced a multi-year, strategic collaboration to enable a paradigm shift for system validation of complex networking system-on-chips (SoCs) using emulation and a virtual tester.
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Cadence Delivers Portable Test and Stimulus Methodology and Library (Wednesday Jul. 17, 2019)
Cadence today announced delivery of the Accellera Portable Test and Stimulus Specification (PSS) 1.0-compliant implementation of the popular Cadence® Perspec™ System Methodology Library (SML) and methodology documentation.
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Pioneer Micro Technology Launches Silvaco PDK for its 0.35 um Silicon Foundry CMOS Process (Wednesday Jul. 17, 2019)
Silvaco Japan Co., Ltd. today announced that Pioneer Micro Technology Corp. (PMT) has begun providing a Process Development Kit (PDK) for Silvaco tool users targeting the manufacture of IC designs in PMT’s 0.35 µm CMOS process technology.
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Synopsys Awarded DARPA ERI Contract Extension for Analog/Mixed-Signal Emulation Technology Innovation (Monday Jul. 15, 2019)
Synopsys today announced a contract extension from the Defense Advanced Research Projects Agency (DARPA) for the Posh Open Source Hardware (POSH) program to continue innovations in analog/mixed-signal (AMS) verification as part of the second phase of the Electronics Resurgence Initiative (ERI), in partnership with Lockheed Martin.
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NSITEXE Accelerates Delivery of Data Flow Processor IP for Automotive and Industrial Applications Using the Cadence Digital Design Full Flow (Friday Jul. 12, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that NSITEXE, Inc. deployed the Cadence® digital design full flow to accelerate the delivery of its high-efficiency, high-quality data flow processor (DFP) IP for automotive and industrial applications.
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The MOSIS Service Selects Synopsys' IC Validator for Large-scale FinFET SoCs (Thursday Jul. 11, 2019)
Synopsys today announced that The MOSIS Service, a leading provider of Multi-Project Wafers, has selected Synopsys' IC Validator tool for physical verification signoff.
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IC Compiler II 2019 Extends Runtime and QoR Leadership with 2X Faster Throughput and 10% Lower Total Power (Thursday Jul. 11, 2019)
Synopsys today announced immediate availability of the latest release of its flagship IC Compiler™ II place-and-route system that includes several new innovative technologies to deliver superior quality-of-results (QoR) and fastest time-to-results (TTR) for the next wave of leading-edge designs across a wide range of vertical markets
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Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology (Wednesday Jul. 03, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® digital full flow has achieved certification for the Samsung Foundry 5nm Low-Power Early (5LPE) process with Extreme Ultraviolet (EUV) lithography technology.
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Samsung Accelerates New Product Ramp for 7nm Technology Node Using Synopsys' Yield Explorer (Tuesday Jul. 02, 2019)
Using the secure data exchange mechanism in Yield Explorer, Samsung is able to share the data required for yield analysis, such as chip design, fab, and test, with its customers while maintaining the confidentiality of proprietary information from each party.
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Avery Design Systems Announces SimRegress and SimCompare (Monday Jul. 01, 2019)
Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimRegress and SimCompare for improved simulation verification productivity.
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InAccel release world's first FPGA orchestrator (Wednesday Jun. 26, 2019)
InAccel, a start-up company specialized on accelerators for machine learning, has released today the latest version of the Coral FPGA resource manager that allows the software community to instantiate and utilize a cluster of FPGAs with the same easy as invoking typical software functions.
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Mentor's Veloce Strato emulation platform selected by Iluvatar CoreX for verification of AI chips and software (Wednesday Jun. 26, 2019)
Mentor, a Siemens business, today announced that artificial intelligence (AI) silicon specialist Iluvatar CoreX has standardized on the Veloce™ Strato emulation platform for the verification of their AI cloud training system-on-chip (SoC) chipset and proprietary software platform.
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Real Intent Announces 10X+ Speedup & 5X Capacity Improvement for Ascent AutoFormal Automatic RTL Verification (Wednesday Jun. 26, 2019)
Real Intent, Inc., today announced that Ascent AutoFormal automatic RTL verification tool has been improved to provide 10X+ performance gains and analyze 5X larger designs when compared to the previous version.
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NanoSemi Relies on OneSpin Automated Formal Verification Tools to Verify SystemC Designs for 5G ASICs (Wednesday Jun. 26, 2019)
OneSpin® Solutions today announced NanoSemi Inc. deployed its formal verification solutions to verify its machine learning-based intellectual property (IP) for 5G and Wi-Fi applications.
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Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development (Wednesday Jun. 19, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Acacia Communications, Inc. has adopted the Cadence® Palladium® Z1 Enterprise Emulation Platform to accelerate the development of its DSP ASICs for optical networking applications.
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IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks (Wednesday Jun. 12, 2019)
ynopsys, Inc. (Nasdaq: SNPS) today announced that its innovative IC Compiler™ II place-and-route solution with Advanced Fusion technologies has been deployed at Juniper Networks, where it delivered better power and area results.
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Imperas and Metrics Collaborate to Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator (Tuesday Jun. 11, 2019)
Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the collaboration with Metrics, working on the verification challenges required for RISC-V cores to achieve the required tape-out-ready quality for broad adoption by silicon designers.
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Space Codesign Systems Announces Support of Zynq UltraScale+ MPSoC (Tuesday Jun. 11, 2019)
Space Codesign Systems announces full system compilation for Xilinx Zynq UltraScale+ MPSoC. The new version of Space Codesign’s tool enables system designers to prototype on the whole range of the Zynq family.
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Efabless Collaborates with GLOBALFOUNDRIES to Enable New IP Development Models for Emerging Applications (Thursday Jun. 06, 2019)
Efabless, a crowdsourcing design platform for custom silicon, today announced a joint relationship with GLOBALFOUNDRIES (GF) that will extend Efabless’ design platform, Chiplicity, to include select technology nodes from GF.
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Faraday Adopts Synopsys SpyGlass Design Handoff Kit to Ensure High Design Quality (Wednesday Jun. 05, 2019)
Synopsys today announced that Faraday Technology Corporation, a leading fabless ASIC and IP provider, has adopted Synopsys' SpyGlass® Design Handoff Kit. Faraday has deployed the SpyGlass Design Handoff Kit to ensure ASIC designs meet design quality requirements before initiating ASIC design service and production.
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Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs (Wednesday Jun. 05, 2019)
Cadence today announced that Socionext used the Cadence® full-flow digital and signoff tools for the successful production tapeout of its latest large, 16nm ASIC chip and has built a design environment for its 7nm designs.
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Synopsys Fusion Design Platform First to be Certified by Samsung Foundry for 5LPE Process with EUV Technology (Tuesday Jun. 04, 2019)
Synopsys today announced that Samsung Electronics has certified the Synopsys Fusion Design Platform™ for Samsung's 5-nanometer (nm) Low-Power Early (LPE) process with Extreme Ultraviolet (EUV) lithography technology.
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Cadence Expands Customer-Managed Cloud Options with New Cloud Passport Partner Program (Tuesday Jun. 04, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the launch of its new Cadence® Cloud Passport Partner Program to give customers a proven and easier path to the cloud when their internal IT teams desire assistance.
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Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy (Tuesday Jun. 04, 2019)
Cadence today announced the Cadence® Spectre® X Simulator, a massively parallel circuit simulator designed to provide up to 10X performance gains, while maintaining the golden accuracy customers have come to expect from 25 years of Spectre industry leadership in analog, mixed-signal and RF applications.
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Silvaco and Si2 Release Unique, Free 15nm Open-Source Digital Cell Library (Monday Jun. 03, 2019)
Silvaco today announced that it is providing an open-source, 15nm standard-cell library to Silicon Integration Initiative. The library is available to Si2 members and universities at no fee under the Apache-2.0 open source license agreement.
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Mentor sets new software scaling benchmark for Semiconductor Design Workload on Microsoft Azure (Monday Jun. 03, 2019)
Mentor, a Siemens business, today announced that the Calibre™ platform Physical Verification Suite has achieved a new standard for electronic design automation (EDA) software scalability on the Microsoft Azure cloud platform.
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Avery Design Systems Announces SimCluster GLS to Accelerate Gate-Level Sign-Off Simulations (Friday May. 31, 2019)
Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimCluster GLS that performs gate-level parallel simulation to achieve 3-5X speed up of sign-off simulations.
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Avery Design Systems Announces SymXprop for X Accurate RTL Simulation (Friday May. 31, 2019)
Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SymXprop that performs high accuracy semi-formal based RTL X handling to eliminate the inherent inaccuracies in logic simulators.
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Synopsys Extends Leadership with Enhanced Verification Continuum Platform (Thursday May. 30, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced a new release of its Verification Continuum™ Platform with new native integrations across verification tools, enabling up to 5X higher verification performance.
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Avatar Integrated Systems Physical Implementation Tool Certified on TSMC 7nm FinFET Process (Tuesday May. 21, 2019)
Avatar Integrated Systems, a leader in next generation physical design solutions, today announced that its Aprisa™ place & route solution has been certified on TSMC's industry-leading 7-nanometer (nm) FinFET technology. Aprisa completed a rigorous certification process to meet the 7nm design rules and requirements.