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Turnkey UWB MAC and PHY platform IP, for FiRa 2.0, CCC Digital Key 3.0, and Radar
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Synopsys Unveils Fusion Compiler, Enabling 20 Percent Higher Quality-of-Results and 2X Faster Time-to-Results (Tuesday Nov. 06, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today unveiled Fusion Compiler™, an innovative RTL-to-GDSII product that enables a new era in digital design implementation.
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FABU America, Developer of SoCs for Autonomous Driving, Selects Agnisys IDesignSpec to Create an Executable Design Specification (Monday Nov. 05, 2018)
Agnisys today announced that FABU America, Inc. has chosen its IDesignSpec™ software for creating executable design specification. FABU America develops intelligent System-on-Chips (SoCs) for autonomous driving.
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AMF Photonics SiP Process Design Kit Available for Synopsys OptoDesigner Photonic IC Layout Solution (Monday Nov. 05, 2018)
Synopsys, Inc. (Nasdaq: SNPS) and Advanced Micro Foundry (AMF) today announced that a new, production-ready process design kit (PDK) based on AMF's silicon photonics (SiP) process is now available in the Synopsys OptoDesigner photonic integrated circuit (PIC) layout software.
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Silicon Valley company unveils the first Artificial Intelligence-based Power Exploration platform for electronics systems and semiconductors (Wednesday Oct. 31, 2018)
Mirabilis Design announced the launch of VisualSim AI-based Power, a system-level power analysis platform for design teams looking to add power requirements to the early stage of product design.
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Synopsys Improves Automotive Functional Safety with Fast Soft-Error Analysis (Monday Oct. 29, 2018)
Synopsys today announced the general availability of new soft-error analysis functionality within its SpyGlass® DFT ADV tool. Output of this analysis directly guides efficient design changes resulting in targeted ISO 26262 functional safety metric improvements at the lowest cost.
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Synopsys Advances Test Fusion Technology with Test Points to Reduce Manufacturing Costs and Boost Quality (Monday Oct. 29, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of Test Fusion technology with new test point functionality, providing design teams with powerful design-for-test (DFT) circuit modifications to reduce silicon test costs by an average of forty percent and increase defect detection while meeting design targets for power, performance, and area
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Real Intent Provides Comprehensive Reset Analysis with Meridian RXV (Monday Oct. 29, 2018)
Real Intent, Inc., a leading provider of SoC and FPGA sign-off verification solutions, today announced Meridian RXV, a new tool to tackle “X” sources and design initialization up-front at the Register Transfer Level (RTL), thereby accelerating reset design, validation and sign-off.
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Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology (Wednesday Oct. 24, 2018)
Cadence today announced that its custom and analog/mixed-signal (AMS) IC design tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology.
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OneSpin Puts Verification on the Move with New PortableCoverage Solution (Wednesday Oct. 24, 2018)
OneSpin® Solutions today announced PortableCoverage™, the first formal verification solution to integrate with all major simulators, coverage databases and viewers, and chip design verification planning tools, enabling users to choose the vendor or multiple vendors of their choice.
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Synopsys Custom Design Platform Delivers Breakthrough Analog Simulation and Fusion Technologies (Tuesday Oct. 23, 2018)
Synopsys today announced that its Custom Design Platform has been enhanced with innovative new FineSim® SPICE circuit simulation and Custom Compiler™ custom layout technologies to address the growing needs of accelerating robust analog/mixed-signal (AMS) designs at advanced process nodes and high-reliability applications.
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Synopsys Custom Compiler Doubles New Customer Adoptions, Introduces New Release (Tuesday Oct. 23, 2018)
Synopsys, Inc. today announced that new customer adoptions of its Custom Compiler™ custom design tool doubled in the past year, driven by the proven benefits of its innovative visually-assisted layout automation technologies.
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Synopsys FineSim SPICE Cuts Analog Simulation Time by 3X (Tuesday Oct. 23, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced major advances in its FineSim® SPICE circuit simulator for analog design. The FineSim SPICE 2018.09 release includes innovative technology that speeds up simulation of leading-edge analog designs by 3X.
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IBM, GLOBALFOUNDRIES Enhance Si2 Unified Power Model Standard (Wednesday Oct. 17, 2018)
Silicon Integration Initiative, an integrated circuit research and development joint venture, announced today that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.
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Synopsys ASIP Designer Tool Speeds Development of Application-Specific Instruction-Set Processors for STMicroelectronics (Tuesday Oct. 16, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced that STMicroelectronics' Microcontroller and Digital IC Groups have chosen Synopsys' ASIP Designer Tool for its key product designs.
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Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing (Tuesday Oct. 16, 2018)
Cadence Palladium Z1 Enterprise Emulation Platform and Perspec System Verifier deliver Arm software compliance tests for Arm-based server SoCs
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Cadence Verification Suite Enabled on Arm-Based HPC Datacenters (Tuesday Oct. 16, 2018)
Cadence Design Systems, Inc. today announced that the Cadence® Verification Suite is now enabled for Arm®-based high-performance computing (HPC) server environments.
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Synopsys Enables Tapeout Success for Early Adopters of Arm Neoverse IP (Tuesday Oct. 16, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced that early collaboration with Arm on its next-generation Arm® Neoverse® family of products targeting cloud-to-edge infrastructure has resulted in successful early adopter tapeout in advanced FinFET process technologies using Synopsys' Design Platform with Fusion Technology™, Verification Continuum™ Platform, and DesignWare® interface IP.
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Synopsys Delivers Platform Architect Ultra to Enable the Next Wave of AI SoCs (Monday Oct. 15, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of its next-generation architecture exploration, analysis, and design solution, Platform Architect™ Ultra, to address the system challenges of artificial intelligence (AI)-enabled system-on-chips (SoCs).
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Mentor releases optimized flow, new fill automation for GLOBALFOUNDRIES' 22FDX IC manufacturing process (Tuesday Oct. 09, 2018)
Mentor, a Siemens business, today announced it has qualified complete solutions from its Calibre® nmPlatform™, Analog FastSPICE™ (AFS)™ Platform, Eldo® Platform and Nitro-SoC place and route system for GLOBALFOUNDRIES' 22FDX Fully-Depleted Silicon-On-Insulator (FD-SOI) integrated circuit (IC) manufacturing processes.
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Synopsys Design Platform Enabled for TSMC's Multi-die 3D-IC Advanced Packaging Technologies (Thursday Oct. 04, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced the Synopsys Design Platform fully supports TSMC's wafer-on-wafer (WoW) direct stacking and chip-on-wafer-on-substrate (CoWoS®) advanced packaging technologies.
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Synopsys Announces Availability of TSMC-certified IC Design Environment in the Cloud (Wednesday Oct. 03, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced it has collaborated with TSMC and leading cloud providers Amazon Web Services (AWS) and Microsoft Azure, to provide a streamlined cloud-based IC design environment on the Synopsys Cloud Solution.
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Cadence Expands its Cloud Portfolio with Delivery of TSMC OIP Virtual Design Environment (Wednesday Oct. 03, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the expansion of the Cadence® Cloud portfolio by providing customers with secure access to TSMC’s new Open Innovation Platform Virtual Design Environment (OIP VDE) to speed system-on-chip (SoC) design
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Cadence Delivers Support for TSMC InFO_MS Advanced Packaging Technologies (Tuesday Oct. 02, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital tools and advanced IC packaging solutions support the new TSMC InFO_MS (InFO with Memory on Substrate) packaging technology.
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Synopsys Digital and Custom Design Platforms Certified on TSMC 5-nm EUV-based Process Technology (Tuesday Oct. 02, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified both the Synopsys Digital and Custom Design Platforms for the latest version of its most advanced, extreme-ultra-violate (EUV)-based, 5-nanometer (nm) process technology.
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Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation (Monday Oct. 01, 2018)
Cadence today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs.
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Chronos Tech Deploys Fabric to Seamlessly Integrate Diverse IPs in Next-Gen System on Chips (Tuesday Sep. 25, 2018)
Chronos Tech has developed groundbreaking solutions for addressing complex IP integration and achieving aggressive Performance, Power and Area (PPA) optimizations.
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Synopsys and SMART Photonics Expand InP-Based PIC Design Automation (Monday Sep. 24, 2018)
Synopsys and SMART Photonics today announced that a new, production-ready process design kit (PDK) based on SMART Photonics' Indium Phosphide (InP) process is now available in Synopsys' OptSim™ Circuit tool to support InP-based photonic integrated circuit (PIC) design and simulation.
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Cadence Achieves Amazon Web Services Industrial Software Competency Status for Its Cloud-Hosted Design Solution (Tuesday Sep. 18, 2018)
Cadence today announced that its Cloud-Hosted Design Solution has undergone rigorous technical validation and achieved Amazon Web Services (AWS) Industrial Software Competency status.
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Graphcore Uses Synopsys Design Platform to Implement Colossus Chip to Accelerate AI Computing (Tuesday Sep. 18, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Graphcore has used the Synopsys Design Platform to successfully implement its Colossus™ intelligent processing unit (IPU) to accelerate artificial intelligence (AI) computing compared to existing processors (CPUs and GPUs).
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Cadence Full-Flow Digital Tool Suite Achieves GLOBALFOUNDRIES 22FDX Certification (Friday Aug. 31, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital tool suite has achieved certification for the GLOBALFOUNDRIES (GF) 22FDX® process technology. The GF certification process was completed using the Cadence® Tensilica® Fusion F1 DSP, which targets internet of things (IoT) and wearables applications.