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IP / SOC Products News

• Rambus, PLDA and Avery Design Announce Comprehensive PCIe 4.0 Solution (Thursday May. 18, 2017)
  Rambus today announced it is collaborating with PLDA, the industry leader in PCI Express® controller IP solutions, and Avery Design Systems Inc., an innovator in functional verification productivity solutions, to offer a comprehensive, silicon-proven PCI Express (PCIe) 4.0 solution, with backward compatibility to PCIe 3.0 and 2.0.
  
  
• Alma Technologies Introduces an Online Tool for Comparison of Image Compression Standards (Wednesday May. 17, 2017)
  An online tool for back-to-back comparison of the image compression standards implemented by our IP cores is now available on our website. The Bit Accurate Models of the respective image compression cores are used to encode / decode a user supplied test image, in order to evaluate and compare their actual performance.
  
  
• Faraday Introduces UrLib+ Add-on Library on UMC 40LP Process (Tuesday May. 16, 2017)
  Faraday today introduced its new UrLib+™ add-on library for the third-party library on UMC 40LP process technology. UrLib+ is a library package, featuring extra sets of cells for optimized PPA (Power/Performance/Area), yield controllability, clock tree noise reduction, robust ESD protection, and lower ECO cost over the traditional physical libraries.
  
  
• eMemory Taps into IoT Markets with its Game-Changing Security IP (Monday May. 15, 2017)
  As Physical Unclonable Functions (PUFs) have become an increasingly popular security technology, eMemory (TPE:3529) today announced the launch of NeoPUF, a game-changing IP innovation which equips every single chip with its own unique “fingerprint”, to capitalize on the growing security demand among IoT applications.
  
  
• Imagination announces first PowerVR Series8XT IP core based on new Furian GPU architecture (Wednesday May. 10, 2017)
  Imagination Technologies (IMG.L) announces the first GPU IP core based on its new PowerVR Furian architecture, the Series8XT GT8525. Furian is designed to enable a new generation of consumer devices to deliver high-resolution, immersive graphics content and data computation for sustained time periods within mobile power budgets.
  
  
• Andes, First Mainstream CPU IP Provider to Adopt RISC-V, Expands Product Line with New 64bit Processor IP (Wednesday May. 10, 2017)
  Andes Technology today announced a new generation of the AndeStar™ architecture. In the process, Andes becomes the first mainstream CPU IP provider to adopt RISC-V, the open RISC Instruction Set Architecture (ISA) developed at the University of California Berkeley.
  
  
• Sonics And Northwest Logic Partner On High Throughput Memory Subsytem Solutions (Tuesday May. 09, 2017)
  Sonics and Northwest Logic today announced their partnership to deliver high throughput memory subsystem solutions for complex System-On-Chip (SOC) designs.
  
  
• Credo Unveils Robust Portfolio of 56G and 112G PAM-4 PHY Connectivity Solutions (Monday May. 08, 2017)
  Credo Semiconductor today announced a comprehensive portfolio of 56G and 112G PAM-4 PHY devices, enabling connectivity for enterprise, hyperscale datacenter, and service provider networks.
  
  
• SiFive Launches CPU IP Industry into the Cloud with New RISC-V Cores and an Easy Online Business Model (Thursday May. 04, 2017)
  SiFive, the company founded by the inventors of the free and open RISC-V instruction set architecture (ISA), today announced the immediate availability of its Coreplex IP, the fastest and easiest way to license RISC-V cores.
  
  
• Hitek Announces Ultra Low Latency 10G Ethernet FPGA IP Core Integrated with Solarflare SFA7942Q AOE (Thursday May. 04, 2017)
  Hitek Systems, a leading FPGA IP core development and FPGA / hardware design services firm, announced the availability of the industry leading Ultra Low Latency 10Gbps Ethernet FPGA IP Core solution integrated with the Solarflare® SFA7942Q ApplicationOnload™ Engine (AOE).
  
  
• VeriSilicon's Vivante VIP8000 Neural Network Processor IP Delivers Over 3 Tera MACs Per Second (Wednesday May. 03, 2017)
  VeriSilicon Holdings Co., Ltd. (VeriSilicon), a Silicon Platform as a Service (SiPaaS®) company, today announces VIP8000, a highly scalable and programmable processor for computer vision and artificial intelligence.
  
  
• Cadence Introduces First Interface and Verification IP Solution for CCIX to Advance New Class of Datacenter Servers (Tuesday May. 02, 2017)
  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the industry’s first interface and verification IP solution for Cache Coherent Interconnect for Accelerators (CCIX), an open chip-to-chip interconnect standard that advances the development of a new class of server solutions to address the challenging
  
  
• Cadence Unveils Industry's First Neural Network DSP IP for Automotive, Surveillance, Drone and Mobile Markets (Monday May. 01, 2017)
  Cadence today unveiled the Cadence® Tensilica® Vision C5 DSP, the industry’s first standalone, self-contained neural network DSP IP core optimized for vision, radar/lidar and fused-sensor applications with high-availability neural network computational needs.
  
  
• Creonic Starts Wideband Satellite Initiative with Launch of New DVB-S2X IP Cores (Friday Apr. 28, 2017)
  Creonic today announced the launch of multiple IP cores for wideband satellite communication, satisfying current and future requirements of nanosatellites as well as high-throughput satellites (HTS).
  
  
• DMP AI Processor IP "ZIA DV700" Enables AI at the Edge (Friday Apr. 28, 2017)
  DMP today announced the new DMP ZIA™ DV700, a high-performance, low-power AI processor for inference, which extends the DMP ZIA™ product portfolio further into the fast-growing deep learning application areas at the edge.
  
  
• Geon Secure Execution Processor Brings Royalty-Free Protection to IoT Devices (Wednesday Apr. 26, 2017)
  Semiconductor intellectual property provider CAST, Inc. today announced the availability of an IP core that builds secure code execution into a 32-bit processor suitable for embedded systems and Internet of Things devices.
  
  
• Inside Secure releases latest True Random Number Generator providing continuous protection against security threats in IoT and Datacenters (Tuesday Apr. 25, 2017)
  Inside Secure today announces the release of its newest version of TRNG-IP-76, the company’s leading true random number generator (TRNG). TRNG-IP-76 is 50 times more efficient than what’s on the market today, and successfully addresses two of the critical challenges for SoC providers: security and power consumption.
  
  
• eASIC and Mobiveil Announce Flash Reliability Platform (Tuesday Apr. 25, 2017)
  eASIC and Mobiveil today announced that Mobiveil’s Flash Reliability IP is now available for use in the eASIC Nextreme-3S family.
  
  
• Synopsys Extends Portfolio of ASIL Ready ISO 26262 Certified DesignWare IP (Tuesday Apr. 25, 2017)
  Synopsys today announced it has extended its portfolio of ASIL B and D Ready ISO 26262 certified DesignWare® IP to include PCI Express® 3.1 controller and PHY, USB 3.0 controller, MIPI CSI-2 controllers and D-PHY, LPDDR4 PHY, EEPROM and Trim NVM.
  
  
• intoPIX Releases New TICO Encoder and Decoder Cores Supporting UHDTV2 and 8K up to 60fps. (Friday Apr. 21, 2017)
  intoPIX, a leading provider of innovative compression technology, today announces new TICO compression IP-cores managing 8K resolutions. The cores offer unique performances at a very light implementation cost for handling HD, 4K and 8K content.
  
  
• Synopsys Enhances ARC Data Fusion Subsystem with New Audio and High-Performance Sensor Support for Always-On IoT Applications (Thursday Apr. 20, 2017)
  Synopsys today announced it has enhanced its DesignWare® ARC® Data Fusion IP Subsystem with a new suite of tightly coupled interface peripherals including pulse density modulation (PDM), I2S and I3C, as well as an audio processing software library to speed application software development.
  
  
• Arastu Systems Ethernet 10G Digital Switch IP Soft Core for Time-Critical Applications (Wednesday Apr. 19, 2017)
  Time critical applications, such as Trading Stock Exchange’s, Airport Terminals etc. require systems that deliver high throughput with low latency, as negligence even by a millisecond can prove catastrophic for business. Bearing in mind the Industry needs, Arastu Systems, a company that specializes in delivering customized IP solution in the Networking and Memory area, today announced Ethernet 10G Digital Switch IP soft core, which is proven and is readily available for usage.
  
  
• IP-Maker to release new NVMe host IP (Wednesday Apr. 19, 2017)
  IP-Maker is extending its storage IP portfolio with the release of its NVMe host controller for embedded applications. The team has implemented the features of the host NVMe driver as a full hardware IP, providing low latency, low gate count and low power consumption. It can be integrated in a FPGA, and manages the NVMe protocol without any CPU. The IP is available now and has been tested on a Xilinx FPGA.
  
  
• Faraday Delivers V-by-One HS PHY & Controller IP on UMC 28HPCU Process (Wednesday Apr. 19, 2017)
  Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced the availability of the proven V-by-One® HS PHY & Controller IP on UMC 28HPCU process technology.
  
  
• Dolphin Integration announces the availability of the new generation 28 nm SpRAM generator (Monday Apr. 17, 2017)
  Dolphin Integration announces the availability of the Calypso architecture. Calypso is a SpRAM optimized for low-power SoCs in TSMC 28 nm HPM technology.
  
  
• PT13: A compact 8-bit microprocessor IP core for just $1000 (Friday Apr. 14, 2017)
  SingMai have introduced the PT13 IP core, a compact, minimal memory, 8-bit microprocessor, and are offering it for just $1000 with an unlimited time/use license.
  
  
• Eta Compute Debuts with World's Lowest Power Microcontroller IP Targeting Energy Harvesting Segment (Tuesday Apr. 11, 2017)
  Eta Compute announced its flagship solution, EtaCore™, the world’s lowest power microcontroller IP, which operates on the smallest energy harvesting supplies without compromising functionality or performance.
  
  
• ArterisIP Advances Machine Learning SoC Design with Ncore 2.0 Cache Coherent Interconnect and Resilience Package (Friday Apr. 07, 2017)
  ArterisIP today announced the Ncore 2.0 Cache Coherent Interconnect IP and the optional Ncore Resilience Package to accelerate and enhance the creation of next-generation designs for autonomous driving systems and advanced driver assistance systems (ADAS).
  
  
• Open-Silicon Unveils Industry's Highest Performance Interlaken Chip-to-Chip Interface IP (Tuesday Apr. 04, 2017)
  Open-Silicon today announced its eighth-generation Interlaken IP core, supporting up to 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC).
  
  
• Faraday Announces World's Smallest Footprint 40eHV and 40LP SRAM Compiler (Thursday Mar. 30, 2017)
  Faraday Technology today announced the enhancement of its memory compiler IP offerings on both UMC 40eHV and 40LP processes. Based on UMC’s leading-edge 40nm bit cell and Faraday’s design optimization on the peripheral circuit, the newly-launched compilers are able to generate memory instances based on the world’s smallest footprint.