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IP / SOC Products News

• OmniPHY Unveils 25G Backplane SerDes Silicon on TSMC 28nm Technology (Thursday Mar. 30, 2017)
  OmniPHY Inc. today announced silicon availability of its industry-leading, low-latency backplane SerDes PHY which delivers enterprise-class performance in demanding backplane applications.
  
  
• ARM DynamIQ: Expanding the possibilities for artificial intelligence (Tuesday Mar. 21, 2017)
  DynamIQ technology is a monumental shift in multicore microarchitecture for the industry and the foundation for future ARM Cortex-A processors. The flexibility and versatility of DynamIQ will redefine the multi-core experience across a greater range of devices from edge to cloud across a secure, common platform.
  
  
• Synopsys' New High-Performance Secure Module with Cryptography Acceleration Speeds Security Functions by 100x (Monday Mar. 20, 2017)
  Synopsys today announced availability of its new high-performance DesignWare® tRoot H5 Hardware Secure Module (HSM) with Root of Trust, providing designers with a Trusted Execution Environment (TEE) that protects sensitive information and data processing within their system-on-chips (SoCs).
  
  
• Comcores announces commercial availability of a complete Radio-Over-Ethernet and L1 offload solution for fronthaul enabling easy bring up of Ethernet based connectivity in radio systems (Thursday Mar. 16, 2017)
  Comcores ApS, a specialized supplier of silicon intellectual property (SIP) today launched a complete IP solution enabling Radio-Over-Ethernet.
  
  
• Synopsys and TSMC Collaborate to Develop Interface, Analog and Foundation IP for 12-nm FinFET Process (Thursday Mar. 16, 2017)
  Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with TSMC to develop DesignWare® Interface, Analog and Foundation IP for TSMC's 12FFC process.
  
  
• GUC PCIe 3 PHY IP & PLDA EP Controller Combo Passes Compliance Test (Wednesday Mar. 15, 2017)
  A Global Unichip Corp. (GUC) low-power PCIe3 PHY IP that the company coupled with an EP Controller from PLDA and designed to TSMC's 28HPC+ process technology has passed the PCI-SIG Compliance Test.
  
  
• ICE-G3 EPU Adds Cluster Controller to Save More Energy For Complex Chip Power Architectures (Wednesday Mar. 15, 2017)
  Sonics today introduced ICE-G3™, the second product in the Energy Processing Unit (EPU) family based on the ICE-Grain Power Architecture™.
  
  
• Barco Silex and Imagination collaborate on SoC security (Tuesday Mar. 14, 2017)
  Imagination will integrate Barco Silex’ eSecure solution for embedded security into a new Trusted Element (TE) IP product. Imagination’s licensable TE will enhance security for customers’ connected devices.
  
  
• Silicon Creations Delivers 12.7G SERDES PMA for TSMC 40LP Process and PLL IP for TSMC 7nm Process (Tuesday Mar. 14, 2017)
  Silicon Creations today announced availability of several industry leading IPs for advanced TSMC processes including a 40LP 0.25Gb/s to 12.7Gb/s multiprotocol SerDes Physical Medium Attachment (PMA) and multiple 7nm PLL products.
  
  
• PLDA Announces XpressRICH4-AXI PCIe 4.0 IP, Providing a High Performance and Reliable AXI Bridge for SoC designs (Monday Mar. 13, 2017)
  The newest addition to PLDA’s extensive line of advanced PCIe products provides the highest level of PCIe-to-AXI integration, preventing AXI deadlock with ordering rules management, while delivering full PCIe 4.0 performance on an AXI interface
  
  
• Analog Bits Announces Mixed Signal Design Kits for 7nm at TSMC Technology Symposium (Monday Mar. 13, 2017)
  Analog Bits today announced availability of front-end design kits which enable use of low power IP on TSMC's latest 7nm process nodes.
  
  
• Open-Silicon Announces IoT Gateway SoC Platform (Monday Mar. 13, 2017)
  Underscoring its commitment to the IoT market, Open- Silicon today announced the development of an IoT gateway SoC platform that enables complete Spec2Chip development of custom silicon solutions for emerging IoT gateway applications.
  
  
• QuickLogic Releases Aurora Software for Evaluation of ArcticPro eFPGA IP (Monday Mar. 13, 2017)
  QuickLogic today announced that it has released its new Aurora software which enables SoC developers to evaluate the integration of embedded FPGA (eFPGA) IP into devices designed for different GLOBALFOUNDRIES process nodes.
  
  
• Imagination's new PowerVR Furian GPU architecture will deliver captivating and engaging visual and vision experiences (Wednesday Mar. 08, 2017)
  Imagination Technologies (IMG.L) unveils its next-generation PowerVR Furian architecture, an entirely new GPU architecture designed for the evolved graphics and compute needs of next-generation consumer devices.
  
  
• Arteris Announces PIANO 2.0 Automated Interconnect Timing Closure Technology (Wednesday Mar. 08, 2017)
  Arteris today announced its next generation automated interconnect timing solution – the PIANO 2.0 Timing Closure Package. PIANO 2.0 builds on customer silicon experience gathered with FlexNoC Physical™ package to automate interconnect timing closure for both cache coherent and non-coherent subsystems.
  
  
• M31 Deploys a Full Range of IP for TSMC 16nm FFC Process (Wednesday Mar. 08, 2017)
  H.P. Lin, Chairman of M31 Technology today announced that it deploys a full range of silicon IP in TSMC's 16nm FFC (FinFET Compact) process technology. With TSMC's advanced 16nm FFC process technology, M31’s IP solutions help IC customers design cost-effective SoCs with low power consumption, high performance and compact area.
  
  
• eMemory's NeoFuse Implemented in HV Process for OLED Application (Wednesday Mar. 08, 2017)
  eMemory announces today its NeoFuse IP has been extensively implemented in High Voltage(HV) platforms across all process nodes from 0.11um to 40nm in six leading foundries responding to the rising demand for Organic Light Emitting Diode (OLED) display applications.
  
  
• Synopsys Announces Industry's First ASIL D Ready Dual-Core Lockstep Processor IP with Integrated Safety Monitor (Tuesday Mar. 07, 2017)
  Synopsys, Inc. (Nasdaq: SNPS) today announced availability of DesignWare® ARC® EM Safety Island IP, dual-core lockstep processors that simplify development of safety-critical applications and accelerate ISO 26262 certification of automotive system-on-chips (SoCs).
  
  
• Ultra-low power memory generators silicon proven at TSMC 55 nm uLP and uLP eFlash (Monday Mar. 06, 2017)
  The ultra-low power targets of a battery-powered SoC - be it for IoT, Wearables, Wireless audio, BLE, SmartHome, Sensor hubs, Wireless automotive, MCUs... - now benefit from the widest panoply of low-power and dense memories proven to safely operate down to 0.81 V and to retain data down to 0.6 V.
  
  
• AMPHION releases 2 extended performance variants of its highly successful HEVC/H.265 'Malone' video decoder IP core (Monday Mar. 06, 2017)
  Amphion Semiconductor today announced the immediate availability of 2 extended performance variants of its highly successful HEVC/H.265 ‘Malone’ video decoder core for SoC implementation.
  
  
• High-Performance Computing gets more energy-efficient data transfer (Thursday Mar. 02, 2017)
  The 3D-NoC network-on-chip developed by Leti, STMicroelectronics, and Mentor Graphics under a project coordinated by IRT Nanoelec offers 20% to 40% less energy consumption and higher speeds than other NoCs.
  
  
• NetSpeed Gains ISO 26262 Certification, ASIL-D Ready, for Its Interconnect IP (Wednesday Mar. 01, 2017)
  NetSpeed Systems Inc., announced today that its interconnect IP portfolio is now certified for the ISO 26262 automotive functional safety standard. SGS-TÜV Saar GmbH, an independent accredited assessor, certified the IP in accordance with ISO 26262, chapter 5.9, making it the first interconnect IP to achieve the highest level of automotive functional safety for both coherent and non-coherent systems.
  
  
• CEVA and ASTRI Unveil Dragonfly NB1, a Licensable NB-IoT Solution For Cost and Power-Sensitive LTE IoT Devices (Monday Feb. 27, 2017)
  CEVAand Hong Kong Applied Science and Technology Research Institute Company Limited (ASTRI) today introduced Dragonfly NB1, a comprehensive cost- and power-optimized NB-IoT solution aimed at streamlining the development of LTE IoT devices.
  
  
• CommSolid Unveils Market's First Integration-Ready NarrowBand-IoT Modem IP Solution (Friday Feb. 24, 2017)
  CommSolid, the cellular IoT IP company, presents CSN130, the market’s first integration-ready NarrowBand-IoT IP (Intellectual Property) solution, at the Mobile World Congress 2017.
  
  
• CEVA Introduces the World's Most Advanced Communication DSP, Providing Cutting-Edge Performance for Multi-Gigabit Class Connectivity (Thursday Feb. 23, 2017)
  Capitalizing on the company's long-standing relationships with world-leading wireless vendors and its unique expertise in DSP architecture design, the CEVA-XC12 is purpose-built from the ground up to solve the most critical challenges of efficiently implementing 5G, gigabit LTE, MU-MIMO Wi-Fi and other multi-gigabit modems.
  
  
• SST Announces Qualification of Embedded SuperFlash on 110 nm CMOS Process (Wednesday Feb. 22, 2017)
  Microchip Technology, through its Silicon Storage Technology (SST) subsidiary, announced today qualification and availability of SST’s third-generation embedded SuperFlash® (ESF3) non-volatile memory (NVM) on 110 nm Complementary Metal-Oxide-Semiconductor (CMOS) platform.
  
  
• First Scalable Wi-Fi HaLow MAC from Methods2Business Built with Cadence Tensilica DSP (Tuesday Feb. 21, 2017)
  Cadence today announced that its Cadence® Tensilica® Fusion F1 DSP is part of the latest Methods2Business (M2B) Wi-Fi HaLow™ MAC IP offering. The licensable IP targets SoCs designed for battery-powered sensor nodes used in smart home, smart city and industrial applications.
  
  
• Cadence Collaborates with CommSolid to Address the Cellular IoT Market with New NB-IoT Baseband IP (Tuesday Feb. 21, 2017)
  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its collaboration with CommSolid, the cellular internet of things (IoT) company, to address the fast growing cellular IoT market with new baseband IP tailored for ultra-low power cellular communication compliant with 3GPP’s NarrowBand IoT (NB-IoT) communications standard.
  
  
• Extending 2 to 5 times the operation time of your battery-powered SoC (Monday Feb. 13, 2017)
  Allowing devices to run on the same battery for years rather than months partakes in enhancing significantly end-user satisfaction. Numerous wireless communication SoC, whether BLE, Zigbee, Sigfox, LoRa, M2M 4G…, have a duty cycle such that the power consumption in sleep mode dominates the overall current drawn from the battery. For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is critical.
  
  
• StreamDSP Serial FPDP Now Supports Xilinx UltraScale+ and Altera Stratix-10 FPGAs (Monday Feb. 13, 2017)
  StreamDSP Announces sFPDP (VITA 17.1) support for Xilinx UltraScale+ and Altera Stratix-10 FPGAs in the their latest v5.4 release