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IP / SOC Products News

• Smartlogic Announces PCI Express Multichannel DMA IP Core optimized for Video Streaming (Friday Oct. 14, 2016)
  The new release of the Multichannel DMA IP Core for PCI Express® contains important features that greatly simplify the DMA transmission of several independent videodatastreams and supports the Xilinx 7 and Ultrascale FPGAs.
  
  
• Imagination rolls out new 'Heterogeneous Inside & Out' MIPS CPU (Wednesday Oct. 12, 2016)
  Imagination Technologies (IMG.L) announces the new MIPS Warrior I-class I6500 CPU, a multi-threaded, multi-core, multi-cluster design that delivers new levels of system efficiency and scalable computing for many-core heterogeneous designs.
  
  
• Faraday's PowerSlash IP Now Available on UMC's 55nm Ultra-Low-Power IoT Platform (Wednesday Oct. 12, 2016)
  Faraday Technology and UMC today announced the availability of Faraday’s PowerSlash™ fundamental IP cells on UMC’s 55nm ultra-low-power process (55ULP) technology.
  
  
• Achronix announces immediate availability of Speedcore embedded FPGA IP for SoC acceleration (Tuesday Oct. 11, 2016)
  Achronix today announced the immediate availability of its Speedcore™ embedded FPGA (eFPGA) IP for integration into customers’ SoCs. Speedcore is designed for compute and network acceleration applications and is based on the same high-performance architecture that is in Achronix’s Speedster™22i FPGAs that have been shipping in production since 2013.
  
  
• Cortus Launches High Performance Dual-Issue IP Core for Embedded Applications (Tuesday Oct. 11, 2016)
  Cortus announced the release of the APS29 - a high performance, dual issue version of its APS25 IP core today. This is the fourth in a family of products based on the Cortus v2 instruction set.
  
  
• Kilopass Delivers 'Refresh' on DRAM Technology (Tuesday Oct. 11, 2016)
  Kilopass today unveiled its Vertical Layered Thyristor (VLT) technology for DRAM applications. VLT eliminates the need for DRAM refresh, is compatible with existing process technologies and offers significant other benefits including lower power, better area efficiency and compatibility.
  
  
• CEVA Introduces Lightweight Multi-Purpose Processor for the Massive Internet of Things (Monday Oct. 10, 2016)
  CEVA today introduced a new lightweight, multi-purpose, processor IP core to streamline the design of cellular-enabled low data rate industrial and consumer loT devices.
  
  
• OmniPhy Announces 1000Base-T1 "Gigabit" Automotive Ethernet Silicon IP Development (Thursday Oct. 06, 2016)
  OmniPhy today announced the availability of a Gigabit automotive Ethernet PHY on an advanced process technology node. The design implements the automotive Ethernet 1000Base-T1 standard spearheaded by the I.E.E.E. through 802.3bp initiative.
  
  
• Accelerate SHA-3 Cryptographic Hash Processing with New Hardware IP Core (Wednesday Oct. 05, 2016)
  A new intellectual property core supports the latest standard for protecting the integrity of electronic transmissions, Secure Hash Algorithm-3 (SHA-3), in a flexible, high-throughput, area-efficient hardware accelerator.
  
  
• NetSpeed Releases Gemini 3.0 Cache-Coherent NoC IP to Supercharge Heterogeneous SoC Designs (Thursday Sep. 29, 2016)
  NetSpeed Systems Inc., announced today the release of its Gemini 3.0 cache-coherent network-on-chip IP that maximizes the performance of heterogeneous multicore system-on-chip (SoC) designs for cloud computing, automotive, mobile and IoT applications.
  
  
• INVECAS and GLOBALFOUNDRIES Announce Availability of Advanced 14nm FinFET Design IP Library for High-Performance Computing, Networking, and High-End Mobile Applications (Thursday Sep. 29, 2016)
  INVECAS and GLOBALFOUNDRIES today announced the availability of foundation IP for GLOBALFOUNDRIES’ 14nm FinFET technology. The silicon-proven IP from INVECAS is optimized for the performance, power, and area requirements of high-performance “all-the-time” applications such as high-end smartphones, networking, server, and graphics processors.
  
  
• Open-Silicon Tapes Out Industry's First High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in 16nm FF+ (Wednesday Sep. 28, 2016)
  Open-Silicon, a system-optimized ASIC solution provider, today announced it has successfully taped out the industry’s first High Bandwidth Memory (HBM2) IP subsystem in TSMC’s 16nm FF+ process in combination with TSMC’s CoWoS® 2.5D silicon interposer technology
  
  
• Cadence Announces General Availability of Tensilica Xtensa LX7 Processor Architecture, Increasing Floating-Point Scalability with 2 to 64 FLOPS/Cycle (Tuesday Sep. 27, 2016)
  
  
  
• Fifth-Generation CEVA Imaging & Vision Technology Simplifies Delivery of Powerful Deep Learning Solutions on Low-Power Embedded Devices (Tuesday Sep. 27, 2016)
  A comprehensive, scalable, integrated hardware and software silicon IP platform that is centered around a new imaging and vision DSP – the CEVA-XM6 - allows developers to efficiently harness the power of neural networks and machine vision for smartphones, autonomous vehicles, surveillance, robots, drones and other camera-enabled smart devices.
  
  
• ARM System IP boosts SoC performance from edge to cloud (Tuesday Sep. 27, 2016)
  ARM has released new on-chip interconnect technology delivering the scalability, performance and efficiency demanded across multiple markets including 5G networks, data center infrastructure, HPC, automotive and industrial systems
  
  
• DCAN FD, A Configurable CAN Bus Controller with Flexible Data-Rate Targets Autonomous Cars & ADAS Systems (Monday Sep. 26, 2016)
  Digital Core Design has introduced the newest IP Core. The DCAN FD IP Core is a configurable CAN Bus controller with Flexible Data-Rate. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate) in accordance to ISO 11898-1:2015.
  
  
• PLDA Announces a Full Set of Solutions to Immediately Enable PCIe 4.0 Design Success (Thursday Sep. 22, 2016)
  PLDA, today announced a full set of solutions allowing designers to create products optimized for PCIe® 4.0 now. PCIe 4.0 motherboards are not expected to be obtainable until 2017, but when they become available, the market will expect access to applications and components that can take advantage of PCIe 4.0’s speed and agility.
  
  
• Synopsys Foundation IP Meets Stringent Automotive AEC-Q100 Grade 1 Temperature Requirements for TSMC 16FFC and 28HPC+ Processes (Wednesday Sep. 21, 2016)
  Synopsys, Inc. (Nasdaq: SNPS) today announced that its DesignWare® Foundation IP, including Logic Libraries and Embedded Memories, meets stringent automotive AEC-Q100 Grade 1 temperature requirements on the TSMC 16-nanometer FinFET Compact (16FFC) and 28-nm High-Performance Compact+ (28HPC+) processes.
  
  
• Cadence Delivers IP for Automotive Applications with TSMC's Advanced 16nm FinFET C Process (Tuesday Sep. 20, 2016)
  Cadence today announced a broad portfolio of Cadence® interface and Denali® memory IP solutions for automotive applications supporting TSMC’s 16nm FinFET Compact (16FFC) process.
  
  
• Synopsys Delivers Complete DesignWare Bluetooth Low Energy IP Solution with Link Layer and PHY on TSMC 40ULP Process for IoT SoCs (Tuesday Sep. 20, 2016)
  Synopsys today announced the immediate availability of its complete DesignWare® Bluetooth® Low Energy IP solution consisting of the Link Layer and PHY on TSMC's 40-nanometer (nm) ultra-low-power (ULP) process.
  
  
• ARM enables autonomous vehicles with its most advanced safety processor (Tuesday Sep. 20, 2016)
  ARM has launched a new real-time processor with advanced safety features for autonomous vehicles and medical and industrial robots. The ARM Cortex-R52 was designed to address functional safety in systems that must comply with ISO 26262 ASIL D and IEC 61508 SIL 3, the most stringent safety standards in the automotive and industrial markets.
  
  
• M31 Technology Develops Complete MIPI PHY Solution Targeting Mobile Device Market (Tuesday Sep. 20, 2016)
  M31 Technology Corporation, a global Silicon Intellectual Property (IP) boutique, today announced it has developed the new generation of MIPI M-PHY and will provide a complete set of MIPI PHY solutions to meet the needs of the mobile device market.
  
  
• Synopsys and TSMC Collaborate on Development of Interface and Foundation IP for 7-nm FinFET Process (Monday Sep. 19, 2016)
  Synopsys today announced the successful tapeout of multiple customer test chips with DesignWare® Logic Libraries and Embedded Memories for TSMC's 7-nanometer (nm) FinFET process.
  
  
• Cache Controller Core from CAST Augments Cache-Less 32-bit Processors (Monday Sep. 19, 2016)
  A cache memory controller IP core available from semiconductor intellectual property provider CAST, Inc. brings cost- and resource-effective improvements in performance, bandwidth, and function to systems using cache-less 32-bit processors.
  
  
• Chevin Technology releases 25G Ultra Low Latency MAC/PCS for Xilinx Virtex UltraScale FPGAs (Thursday Sep. 15, 2016)
  Chevin Technology Limited is excited to add the Low Latency 25Gbit/s MAC/PCS IP product to its existing range of Ultra Low Latency IP cores. The 25G LL MAC/PCS combines Chevin Technology’s 25GMAC and 25GPCS IP cores to significantly increase the efficiency and rate of data transfer by providing lowest possible latency.
  
  
• Synopsys Introduces ARC Security Processors for Low-Power Embedded Applications (Monday Sep. 12, 2016)
  Synopsys today announced availability of the DesignWare®ARC® SEM110 and SEM120D security processors for low-power, embedded applications such as smart metering, NFC payment and embedded SIMs.
  
  
• Imagination teams with SaberTek and Mymo Wireless to deliver end-to-end licensable IP for LTE CAT1/0 (Wednesday Sep. 07, 2016)
  Imagination Technologies (IMG.L) announces that it has teamed with Mymo Wireless and SaberTek to provide a complete end-to-end licensable silicon IP for LTE CAT1/0. The offering provides joint customers a low-risk, cost-effective solution that is optimized for low data rate applications such as asset tracking, fleet management, security and surveillance, point of sale, health monitoring, smart metering, and a growing number of other IoT applications.
  
  
• Boost Valley Announces its first FPGA proven IP - HDMI-CEC 2.0 Controller IP (Wednesday Sep. 07, 2016)
  Today, Boost Valley announces its first step into the IP market introducing its first FPGA proven IP – HDMI-CEC 2.0 Controller. The Consumer Electronics Control (HDMI-CEC) is a 500 Mb/s bi-directional serial bus designed to control multiple HDMI devices with a single remote-control.
  
  
• Moortec Announce Embedded Process Monitor on TSMC 16FF+ (Wednesday Aug. 31, 2016)
  Moortec Semiconductor, specialists in Process, Voltage and Temperature (PVT) sensors announce the availability of their Embedded Process Monitor on TSMC’s 16nm FinFET+ process.
  
  
• World's first Chinese AVS2 decoder IP release by Chips&Media (Wednesday Aug. 31, 2016)
  Chips&Media Inc. released today its new AVS2 hardware decoder IP, WAVE515 which is one of the 2nd generation UHD video IP WAVE5 series.