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3.3V Wide-Range General Purpose I/O Pad Set

USB 3.1 Type-C / DisplayPort PHY in Samsung 5LPE

• Supports 10 Gbps and 5 Gbps data rates;
• Supports RBR, HBR1, HBR2 and HBR3 data rates;
• Low active and standby power

12bits, 1Gsps, Self-Calibrating Current Steering IQDAC

• Metal Scheme: 11M_3Mx_6Dx_1Gx_1Iz_LB
• 12b Resolution, Fs = 1Gsps
• Programmable 20mA Differential Current source

LPDDR5 Controller Core

PHY IP for PCIe 5.0 on Samsung 8LPP

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

PHY IP for PCIe 5.0 on TSMC N6

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

LPDDR5/LPDDR4 combo PHY on 14nm, 12nm

• JESD209-5A(LPDDR5), JESD209-4C(LPDDR4), JESD209-4-1(LPDDR4X) compliant
• Operating speed up to 6400Mbps in LPDDR5, 4266Mbps in LPDDR4X
• Multiple DFICLK : CK :WCK ratios

MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI

• 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process

PCIE 5.0 PHY in Samsung 10/8LPP, SMIC 14SFE/SF+, and TSMC 12FFC

• Support 32Gbps serial data transmission rate
• Utilizes 8-bit, 16-bit or 32-bit parallel interface to transmit and receive data

USB-C 3.2/DisplayPort PHY IP for Samsung 4LPE

• Samsung 4LPe
• USB-IF certified DesignWare USB 3.2 solution
• VESA certified DesignWare DisplayPort 1.4 Tx solution

Analog I/O + ESD protection for Die-2-die interfaces

• Analog I/Os
• ESD Power protection
• Ground pads

1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes

• High speed performance
• Low power architecture
• Sub-sampling clock multiplier