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New Silicon IP
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DesignWare USB-C 3.2/DisplayPort PHY IP for Samsung 4LPE
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Analog I/O + ESD protection for Die-2-die interfaces
- Analog I/Os
- ESD Power protection
- Ground pads
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1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- High speed performance
- Low power architecture
- Sub-sampling clock multiplier
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12-bit 640MS/s Dual-Channel IQ ultra-low power DAC on Samsung 28nm FDS
- 28nm Samsung FDS Process, 7 Metals Used
- 1.8V and 1.0V Supplies
- Sampling Rate up to 640MS/s
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Ultra-low quiescent capacitor-less LDO voltage regulator in Samsung Foundries 65nm LFR6LP
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Low-power Power-On-reset design in Samsung Foundries 65nm LFR6LP process
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