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New Silicon IP
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DAC Bias Block
- 28nm Samsung LPP Process, 6 Metals Used
- 1.8V and 1.0V Supplies
- Accurate 1.0V Bandgap Reference
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12bit 1MSPS SAR ADC
- SAMSUNG 65nm CMOS
- Wide Operating Range
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PCIe 4.0 PHY in Samsung 14LPP
- Built-in self-test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
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USB 3.1 PHY (10G/5G)
- Samsung 10LPP x1 OTG, North/South Poly Orientation
- Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
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Four Channel LVDS Serializer
- 25-165 MHz clock support
- Up to 1250 Mbps bandwidth/channel
- Up to 5.0 Gbps data throughput
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USB 2.0 femtoPHY - Samsung 14LPP18 x1, OTG, North/South (vertical) poly orientation
- Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
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