The UDP/IP Hardware Stack / UDP Off-load Engine (UOE) has low latency performance targeting 10/40 GbE high-frequency trading systems. The UDP/IP Hardware Stack / UDP Off-load Engine (UOE) is a Verilog SoC IP Core targeting Xilinx Virtex 7 and Altera Stratix V FPGAs.
- 10/40 Gb wire-line performance with ultra-low latency
- Address Resolution Protocol (ARP) Packet Processor (client/server)with 4-16 entry ARP cache
- IP Packet Processor:
- IP & ICMP (Internet Control Message Protocol) Protocol
- Host IP address filter, IP header checksum check & generator, user selectable Maximum Transmission Unit (MTU), Unicast & Multicast Packet support
- UDP Packet Processor:
- Support for up to 256 UDP Ports
- UDP header checksum check & generator
- High Speed Data Interface to user Host Application
- PHY Controller – control interface to user Host Application
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the UDP/IP Hardware Stack / UDP Off-load Engine (UOE)