12-bit 120MS/s Dual Channel ADC

Features

• TSMC 55nm ULP (Ultra Low Power Process)
• No Analog Options
• 1.2V and 2.5V Supplies
• 12-bit High-Speed SAR Dual-Channel ADC
• Up-to 120MS/s Sampling Rate per Channel
• Internal Bandgap and Voltage Reference Buffers Included
• No External Accurate Reference required
• No External Reference Decoupling required
• Differential Input Signal Range: 1.0Vppdiff
• Outstanding Dynamic Performance:
• 75.0dB SFDR
• -75.0dB THD
• 63.5dB SNR
• 63.1dB SNDR
• 10.2-bit ENOB
• [Noise integrated up-to Nyquist]
• Outstanding Cross-Channel Performance:
• < ±0.1dB Channels Gain Mismatch
• < -75.0dB Crosstalk between Channels
• Ultra-Low Power Dissipation: 27mW
• Compact Die Area: 0.15mm2
• (post optical shrink)

Benefits

• This high-end performance is obtained with a compact die area of 0.15mm2 and dissipating a mere 27mW for the full IP, including both channels converting continuously at 120MS/s.
• The S3ADSIQ120M12BT55ULP does not require any special analog options and can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioural Model (Verilog .v)
• Integration Guidelines and Support
• *Subject to Agreement

Applications

• Connected Consumer Devices
• 802.11ac
• LTE
• DVB
• Home Network
• Wireline Communications
• Imaging

Block Diagram of the 12-bit 120MS/s Dual Channel ADC

• see the entire 12-bit 120MS/s Dual Channel ADC datasheet
• get in contact with 12-bit 120MS/s Dual Channel ADC Supplier